After the 3-D stacking, 3-D-ICs based on through-silicon-vias (TSVs) must be inspected for any TSV defects such as resistive open or bridge defects. In some research studies, several effective testing techniques have been developed such as parallel or serial test architectures, which measure the voltage across a single TSV with a comparator. However, in the current test architectures, hardware overhead and test time are proportional to the number of TSVs. In this paper, we propose a new unified test architecture for screening of TSV defects in 3-D-ICs. Depending on the number of assembled TSVs, the proposed grouping-based test architecture can effectively reduce the cumulative test time and hardware overhead without compromising the test quality.
|Number of pages||5|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 2017 Oct|
Bibliographical noteFunding Information:
Manuscript received February 21, 2016; revised June 2, 2016 and August 24, 2016; accepted September 8, 2016. Date of publication September 20, 2016; date of current version September 14, 2017. This work was supported by the National Research Foundation of Korea through the Korea Government (MSIP) under Grant 2015R1A2A1A13001751. This paper was recommended by Associate Editor N. Nicolici. (Corresponding author: Sungho Kang.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: firstname.lastname@example.org; email@example.com; firstname.lastname@example.org).
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All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering