GRO-TDC with gate-switch-based delay cell halving resolution limit

In this paper, we propose a time-to-digital converter (TDC) with first-order noise-shaping. The proposed gated ring oscillator (GRO)-TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate-switched configuration to solve the charge redistribution problem. The proposed GRO-TDC is designed using a 65-nm process technology, with an area of 0.015 mm ² and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO-TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO-TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively.