In this paper, we present GradPIM, a processingin-memory architecture which accelerates parameter updates of deep neural networks training. As one of processing-in-memory techniques that could be realized in the near future, we propose an incremental, simple architectural design that does not invade the existing memory protocol. Extending DDR4 SDRAM to utilize bank-group parallelism makes our operation designs in processing-in-memory (PIM) module efficient in terms of hardware cost and performance. Our experimental results show that the proposed architecture can improve the performance of DNN training and greatly reduce memory bandwidth requirement while posing only a minimal amount of overhead to the protocol and DRAM area.
|Title of host publication||Proceeding - 27th IEEE International Symposium on High Performance Computer Architecture, HPCA 2021|
|Publisher||IEEE Computer Society|
|Number of pages||14|
|Publication status||Published - 2021 Feb|
|Event||27th Annual IEEE International Symposium on High Performance Computer Architecture, HPCA 2021 - Virtual, Seoul, Korea, Republic of|
Duration: 2021 Feb 27 → 2021 Mar 1
|Name||Proceedings - International Symposium on High-Performance Computer Architecture|
|Conference||27th Annual IEEE International Symposium on High Performance Computer Architecture, HPCA 2021|
|Country/Territory||Korea, Republic of|
|Period||21/2/27 → 21/3/1|
Bibliographical notePublisher Copyright:
© 2021 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture