To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-Test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external lowspeed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-The-fly to perform complicated and hard-To-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.
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© 2015 ETRI.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Computer Science(all)
- Electrical and Electronic Engineering