As the availability of field-programmable gate arrays (FPGAS) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAS differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect the power consumption of FPGA. Therefore, we propose a simulator which is able to estimate the power in consideration of input data. It estimates the power consumption more accurately at a minute level. From the result of experiment, we identify that there is a great gap on power estimation between previous methods and the proposed one.
|Title of host publication||ISOCC 2016 - International SoC Design Conference|
|Subtitle of host publication||Smart SoC for Intelligent Things|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2016 Dec 27|
|Event||13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of|
Duration: 2016 Oct 23 → 2016 Oct 26
|Name||ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things|
|Other||13th International SoC Design Conference, ISOCC 2016|
|Country/Territory||Korea, Republic of|
|Period||16/10/23 → 16/10/26|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2016R1A2B4011799) and by SK-Hynix Semiconductor Inc.
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering