FPGA power estimation simulator for dynamic input data

Taehee You; Jeongbin Kim; Minyoung Im; Eui Young Chung

doi:10.1109/ISOCC.2016.7799824

FPGA power estimation simulator for dynamic input data

Taehee You, Jeongbin Kim, Minyoung Im, Eui Young Chung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

As the availability of field-programmable gate arrays (FPGAS) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAS differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect the power consumption of FPGA. Therefore, we propose a simulator which is able to estimate the power in consideration of input data. It estimates the power consumption more accurately at a minute level. From the result of experiment, we identify that there is a great gap on power estimation between previous methods and the proposed one.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	355-356
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799824
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2016R1A2B4011799) and by SK-Hynix Semiconductor Inc.

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799824

Cite this

You, T., Kim, J., Im, M., & Chung, E. Y. (2016). FPGA power estimation simulator for dynamic input data. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 355-356). [7799824] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799824

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title = "FPGA power estimation simulator for dynamic input data",

abstract = "As the availability of field-programmable gate arrays (FPGAS) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAS differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect the power consumption of FPGA. Therefore, we propose a simulator which is able to estimate the power in consideration of input data. It estimates the power consumption more accurately at a minute level. From the result of experiment, we identify that there is a great gap on power estimation between previous methods and the proposed one.",

author = "Taehee You and Jeongbin Kim and Minyoung Im and Chung, {Eui Young}",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2016R1A2B4011799) and by SK-Hynix Semiconductor Inc. Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

year = "2016",

month = dec,

day = "27",

doi = "10.1109/ISOCC.2016.7799824",

language = "English",

series = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "ISOCC 2016 - International SoC Design Conference",

address = "United States",

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You, T, Kim, J, Im, M & Chung, EY 2016, FPGA power estimation simulator for dynamic input data. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799824, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 355-356, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799824

FPGA power estimation simulator for dynamic input data. / You, Taehee; Kim, Jeongbin; Im, Minyoung et al.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 355-356 7799824 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - FPGA power estimation simulator for dynamic input data

AU - You, Taehee

AU - Kim, Jeongbin

AU - Im, Minyoung

AU - Chung, Eui Young

N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (2016R1A2B4011799) and by SK-Hynix Semiconductor Inc. Publisher Copyright: © 2016 IEEE.

PY - 2016/12/27

Y1 - 2016/12/27

N2 - As the availability of field-programmable gate arrays (FPGAS) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAS differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect the power consumption of FPGA. Therefore, we propose a simulator which is able to estimate the power in consideration of input data. It estimates the power consumption more accurately at a minute level. From the result of experiment, we identify that there is a great gap on power estimation between previous methods and the proposed one.

AB - As the availability of field-programmable gate arrays (FPGAS) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAS differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect the power consumption of FPGA. Therefore, we propose a simulator which is able to estimate the power in consideration of input data. It estimates the power consumption more accurately at a minute level. From the result of experiment, we identify that there is a great gap on power estimation between previous methods and the proposed one.

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M3 - Conference contribution

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T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

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BT - ISOCC 2016 - International SoC Design Conference

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You T, Kim J, Im M, Chung EY. FPGA power estimation simulator for dynamic input data. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 355-356. 7799824. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). doi: 10.1109/ISOCC.2016.7799824

FPGA power estimation simulator for dynamic input data

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