FlashGPU: Placing new flash next to GPU cores

Jie Zhang, Miryeong Kwon, Hyojong Kim, Hyesoon Kim, Myoungsoo Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)


We propose FlashGPU, a new GPU architecture that tightly blends new flash (Z-NAND) with massive GPU cores. Specifically, we replace global memory with Z-NAND that exhibits ultra-low latency. We also architect a flash core to manage request dispatches and address translations underneath L2 cache banks of GPU cores. While Z-NAND is a hundred times faster than conventional 3D-stacked flash, its latency is still longer than DRAM. To address this shortcoming, we propose a dynamic page-placement and buffer manager in Z-NAND subsystems by being aware of bulk and parallel memory access characteristics of GPU applications, thereby offering high-throughput and low-energy consumption behaviors.

Original languageEnglish
Title of host publicationProceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450367257
Publication statusPublished - 2019 Jun 2
Event56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States
Duration: 2019 Jun 22019 Jun 6

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference56th Annual Design Automation Conference, DAC 2019
Country/TerritoryUnited States
CityLas Vegas

Bibliographical note

Publisher Copyright:
© 2019 Association for Computing Machinery.

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation


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