A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.
|Number of pages||2|
|Publication status||Published - 2002 Aug 1|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering