Fast floating-point normalisation unit realised using NOR planes

Kyung Nam Han, Sang Wook Han, Euisik Yoon

Research output: Contribution to journalArticlepeer-review


A new floating-point (FP) normalisation unit scheme is presented, that achieves enhanced performance by merging a leading zero counter (LZC) and a normalisation shifter. The LZC and the shift decoder are combined by using NOR planes to generate control signals directly to the normalisation shifter. The chip has been fabricated with a five-metal 0.18 μm CMOS process and performs the 64 bit FP normalisation within 1.4 ns.

Original languageEnglish
Pages (from-to)857-858
Number of pages2
JournalElectronics Letters
Issue number16
Publication statusPublished - 2002 Aug 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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