Fast area-efficient VLSI adders

Tackdon Han, David A. Carlson

Research output: Chapter in Book/Report/Conference proceedingChapter

1 Citation (Scopus)


In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results we obtain lead to the design of area-time efficient VLSI adders. This is a major goal of our work: to design very low latency addition circuitry that is also area efficient. To this end, we present a new graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, we are able to design VLSI adders having area A = 0(n log n) whose delay time is the lowest possible value, i. e. the fastest possible area-efficient VLSI adder.

Original languageEnglish
Title of host publicationComputer Arithmetic
Subtitle of host publicationVolume I
PublisherWorld Scientific Publishing Co.
Number of pages8
ISBN (Electronic)9789814651578
ISBN (Print)9789814651561
Publication statusPublished - 2015 Jan 1

Bibliographical note

Publisher Copyright:
© 1987 by The Institute of Electrical and Electronics Engineers, Inc.

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)
  • Mathematics(all)


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