Failure bitmap compression method for 3D-IC redundancy analysis

Keewon Cho; Woosung Lee; Jooyoung Kim; Sungho Kang

doi:10.1109/ISOCC.2015.7401724

Failure bitmap compression method for 3D-IC redundancy analysis

Keewon Cho, Woosung Lee, Jooyoung Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

Original language	English
Title of host publication	ISOCC 2015 - International SoC Design Conference
Subtitle of host publication	SoC for Internet of Everything (IoE)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	335-336
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2015.7401724
Publication status	Published - 2016 Feb 8
Event	12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of Duration: 2015 Nov 2 → 2015 Nov 5

Publication series

Name	ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Other

Other	12th International SoC Design Conference, ISOCC 2015
Country/Territory	Korea, Republic of
City	Gyeongju
Period	15/11/2 → 15/11/5

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2015.7401724

Cite this

Cho, K., Lee, W., Kim, J., & Kang, S. (2016). Failure bitmap compression method for 3D-IC redundancy analysis. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) (pp. 335-336). Article 7401724 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2015.7401724

@inproceedings{143924dee29f45898e767cc469743422,

title = "Failure bitmap compression method for 3D-IC redundancy analysis",

abstract = "As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.",

author = "Keewon Cho and Woosung Lee and Jooyoung Kim and Sungho Kang",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 12th International SoC Design Conference, ISOCC 2015 ; Conference date: 02-11-2015 Through 05-11-2015",

year = "2016",

month = feb,

day = "8",

doi = "10.1109/ISOCC.2015.7401724",

language = "English",

series = "ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "335--336",

booktitle = "ISOCC 2015 - International SoC Design Conference",

address = "United States",

}

Cho, K, Lee, W, Kim, J & Kang, S 2016, Failure bitmap compression method for 3D-IC redundancy analysis. in ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)., 7401724, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE), Institute of Electrical and Electronics Engineers Inc., pp. 335-336, 12th International SoC Design Conference, ISOCC 2015, Gyeongju, Korea, Republic of, 15/11/2. https://doi.org/10.1109/ISOCC.2015.7401724

Failure bitmap compression method for 3D-IC redundancy analysis. / Cho, Keewon; Lee, Woosung; Kim, Jooyoung et al.
ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., 2016. p. 335-336 7401724 (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Failure bitmap compression method for 3D-IC redundancy analysis

AU - Cho, Keewon

AU - Lee, Woosung

AU - Kim, Jooyoung

AU - Kang, Sungho

PY - 2016/2/8

Y1 - 2016/2/8

N2 - As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

AB - As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

UR - http://www.scopus.com/inward/record.url?scp=84963861086&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84963861086&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2015.7401724

DO - 10.1109/ISOCC.2015.7401724

M3 - Conference contribution

AN - SCOPUS:84963861086

T3 - ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

SP - 335

EP - 336

BT - ISOCC 2015 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th International SoC Design Conference, ISOCC 2015

Y2 - 2 November 2015 through 5 November 2015

ER -

Cho K, Lee W, Kim J, Kang S. Failure bitmap compression method for 3D-IC redundancy analysis. In ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc. 2016. p. 335-336. 7401724. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)). doi: 10.1109/ISOCC.2015.7401724

Failure bitmap compression method for 3D-IC redundancy analysis

Abstract

Publication series

Other

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this