Failure bitmap compression method for 3D-IC redundancy analysis

Keewon Cho, Woosung Lee, Jooyoung Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution


As the chance of memory faults has increased, many redundancy analysis (RA) techniques are widely used in order to gain a proper manufacturing yield. To find appropriate repair solutions, the external automatic test equipment (ATE) receives the faulty information and stores it into a 2-D failure bitmap. This paper presents a new failure bitmap compression method which utilizes modified run-length codes. The proposed idea can reduce hardware overhead of a failure bitmap while preserving all the faulty information that is needed to get optimal repair rate. Experimental results show that the proposed method can obtain more than 80% of reduction rate in the failure bitmap size.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467393089
Publication statusPublished - 2016 Feb 8
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2015 Nov 22015 Nov 5

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)


Other12th International SoC Design Conference, ISOCC 2015
Country/TerritoryKorea, Republic of

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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