Resiliency is a first-order design concern in modern microprocessor design. Compiler-level Redundant MultiThreading (RMT) schemes are promising because of their capability to detect the manifestation of hardware transient and permanent faults. In this work, we propose EXPERT, a compiler-level RMT scheme which can detect the manifestation of hardware faults in all hardware components. EXPERT transformation generates a checker thread for program main execution thread. These redundant threads execute simultaneously on two physically different cores of a multi-core processor. They perform mostly same computations, however, after each memory write operation committed by the main thread, the checker thread loads back the written data from the memory and checks it against its own locally computed values. If they match, execution continues. Otherwise, the error flag will be raised. Our processor-wide statistical transient and permanent fault injection experiments show that EXPERT error coverage is ∼65x better than the state-of-The-Art scheme.
|Title of host publication||Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 2018 Apr 19|
|Event||2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany|
Duration: 2018 Mar 19 → 2018 Mar 23
|Name||Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018|
|Other||2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018|
|Period||18/3/19 → 18/3/23|
Bibliographical noteFunding Information:
VII. ACKNOWLEDGEMENTS This work was partially supported by funding from NSF CCF 1055094 (CAREER); by global PH.D fellowship program through the NRF funded by the Ministry of Education (NRF-2016H1A2A1909470); by next-generation information computing development program through the NRF funded by the Ministry of Science, ICT, and Future Planning (NRF-2015M3C4A7065522).
© 2018 EDAA.
All Science Journal Classification (ASJC) codes
- Safety, Risk, Reliability and Quality
- Hardware and Architecture
- Information Systems and Management