Equalization scheme analysis for high-density spin transfer torque random access memory

Beomsang Yoo; Taehui Na; Byungkyu Song; Seong Ook Jung; Jung Pill Kim; Seung H. Kang

doi:10.1109/ISOCC.2016.7799752

Equalization scheme analysis for high-density spin transfer torque random access memory

Beomsang Yoo, Taehui Na, Byungkyu Song, Seong Ook Jung, Jung Pill Kim, Seung H. Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	99-100
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799752
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799752

Cite this

Yoo, B., Na, T., Song, B., Jung, S. O., Kim, J. P., & Kang, S. H. (2016). Equalization scheme analysis for high-density spin transfer torque random access memory. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 99-100). Article 7799752 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799752

Yoo, Beomsang ; Na, Taehui ; Song, Byungkyu et al. / Equalization scheme analysis for high-density spin transfer torque random access memory. ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 99-100 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

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title = "Equalization scheme analysis for high-density spin transfer torque random access memory",

abstract = "As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.",

keywords = "Equalization scheme, Nonvolatile memory (NVM), Sensing circuit, Spin transfer torque RAM (STT-RAM)",

author = "Beomsang Yoo and Taehui Na and Byungkyu Song and Jung, {Seong Ook} and Kim, {Jung Pill} and Kang, {Seung H.}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

year = "2016",

month = dec,

day = "27",

doi = "10.1109/ISOCC.2016.7799752",

language = "English",

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Yoo, B, Na, T, Song, B, Jung, SO, Kim, JP & Kang, SH 2016, Equalization scheme analysis for high-density spin transfer torque random access memory. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799752, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 99-100, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799752

Equalization scheme analysis for high-density spin transfer torque random access memory. / Yoo, Beomsang; Na, Taehui; Song, Byungkyu et al.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 99-100 7799752 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Yoo, Beomsang

AU - Na, Taehui

AU - Song, Byungkyu

AU - Jung, Seong Ook

AU - Kim, Jung Pill

AU - Kang, Seung H.

PY - 2016/12/27

Y1 - 2016/12/27

N2 - As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.

AB - As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.

KW - Equalization scheme

KW - Nonvolatile memory (NVM)

KW - Sensing circuit

KW - Spin transfer torque RAM (STT-RAM)

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Yoo B, Na T, Song B, Jung SO, Kim JP, Kang SH. Equalization scheme analysis for high-density spin transfer torque random access memory. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 99-100. 7799752. (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). doi: 10.1109/ISOCC.2016.7799752

Equalization scheme analysis for high-density spin transfer torque random access memory

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