Enhanced prformance in SOI FinFETs with low series resistance by aluminum implant as a solution beyond 22nm node

I. Ok, C. D. Young, W. Y. Loh, T. Ngai, S. Lian, J. Oh, M. P. Rodgers, S. Bennett, H. O. Stamper, D. L. Franca, S. Lin, K. Akarvardar, C. Smith, C. Hobbs, P. Kirsch, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the Schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate stacks. These attributes constitute a simple non-planar cMOS integration sequence for enhancing future high performance technology nodes.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Technology, VLSIT 2010
Pages17-18
Number of pages2
DOIs
Publication statusPublished - 2010
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 2010 Jun 152010 Jun 17

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2010 Symposium on VLSI Technology, VLSIT 2010
Country/TerritoryUnited States
CityHonolulu, HI
Period10/6/1510/6/17

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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