Enhanced algorithm of combining trace and scan signals in post-silicon validation

Kihyuk Han, Joon Sung Yang, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


As the complexity of integrated circuit design increases and production schedules become shorter, the dependency on post-silicon validation for capturing design errors that escape from pre-silicon verification also increases. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for post-silicon validation. Recent research has shown that observability can be enhanced if trace and scan signals are combined together, compared with the debugging scenario where only trace signals are monitored. This paper proposes an enhanced and systematic algorithm for the efficient combination of trace and scan signals to maximize the observability of internal circuit states. Experimental results on benchmark circuits show that the proposed technique provides a higher number of restored states compared to the existing techniques.

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
Publication statusPublished - 2013
Event2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
Duration: 2013 Apr 292013 May 1

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
Country/TerritoryUnited States
CityBerkeley, CA

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering


Dive into the research topics of 'Enhanced algorithm of combining trace and scan signals in post-silicon validation'. Together they form a unique fingerprint.

Cite this