TY - JOUR
T1 - Electrical analysis of bottom gate TFT with novel process architecture
AU - Pak, Sang Hoon
AU - Jeong, Tae Hoon
AU - Kim, Si Joon
AU - Kim, Kyung Ho
AU - Kim, Hyun Jae
PY - 2008
Y1 - 2008
N2 - Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.
AB - Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.
UR - http://www.scopus.com/inward/record.url?scp=85024067349&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85024067349&partnerID=8YFLogxK
U2 - 10.1080/15980316.2008.9652050
DO - 10.1080/15980316.2008.9652050
M3 - Article
AN - SCOPUS:85024067349
SN - 1598-0316
VL - 9
SP - 5
EP - 8
JO - Journal of Information Display
JF - Journal of Information Display
IS - 2
ER -