Efficient path-delay fault simulator for mixed level circuits

Yong Seok Kang; Yong Tae Yim; Sungho Kang

Efficient path-delay fault simulator for mixed level circuits

Yong Seok Kang, Yong Tae Yim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator.

Original language	English
Pages (from-to)	263-266
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication status	Published - 1996
Event	Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: 1996 Sept 23 → 1996 Sept 27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@article{3490ddbbcfe2451ab2cbe57f6a7740e5,

title = "Efficient path-delay fault simulator for mixed level circuits",

abstract = "This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator.",

author = "Kang, {Yong Seok} and Yim, {Yong Tae} and Sungho Kang",

year = "1996",

language = "English",

pages = "263--266",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 23-09-1996 Through 27-09-1996",

}

TY - JOUR

T1 - Efficient path-delay fault simulator for mixed level circuits

AU - Kang, Yong Seok

AU - Yim, Yong Tae

AU - Kang, Sungho

PY - 1996

Y1 - 1996

N2 - This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator.

AB - This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator.

UR - http://www.scopus.com/inward/record.url?scp=0029726965&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029726965&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029726965

SN - 1063-0988

SP - 263

EP - 266

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit

Y2 - 23 September 1996 through 27 September 1996

ER -

Efficient path-delay fault simulator for mixed level circuits

Abstract

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this