Efficient design of symbol detector for MIMO-OFDM based wireless LANs

Noh Seungpyo; Jung Yunho; Kim Jaeseok

doi:10.1109/SIPS.2005.1579833

Efficient design of symbol detector for MIMO-OFDM based wireless LANs

Noh Seungpyo, Jung Yunho, Kim Jaeseok

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18um CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.

Original language	English
Title of host publication	SiPS 2005
Subtitle of host publication	IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings
Pages	25-29
Number of pages	5
DOIs	https://doi.org/10.1109/SIPS.2005.1579833
Publication status	Published - 2005
Event	SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation - Athens, Greece Duration: 2005 Nov 2 → 2005 Nov 4

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume	2005
ISSN (Print)	1520-6130

Other

Other	SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation
Country/Territory	Greece
City	Athens
Period	05/11/2 → 05/11/4

All Science Journal Classification (ASJC) codes

Media Technology
Signal Processing

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10.1109/SIPS.2005.1579833

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Seungpyo, N., Yunho, J., & Jaeseok, K. (2005). Efficient design of symbol detector for MIMO-OFDM based wireless LANs. In SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings (pp. 25-29). Article 1579833 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2005). https://doi.org/10.1109/SIPS.2005.1579833

@inproceedings{e49dab3c61974bd8b84b1ef440f8349e,

title = "Efficient design of symbol detector for MIMO-OFDM based wireless LANs",

abstract = "In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18um CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.",

author = "Noh Seungpyo and Jung Yunho and Kim Jaeseok",

year = "2005",

doi = "10.1109/SIPS.2005.1579833",

language = "English",

isbn = "0780393341",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "25--29",

booktitle = "SiPS 2005",

note = "SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation ; Conference date: 02-11-2005 Through 04-11-2005",

}

Seungpyo, N, Yunho, J & Jaeseok, K 2005, Efficient design of symbol detector for MIMO-OFDM based wireless LANs. in SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings., 1579833, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, vol. 2005, pp. 25-29, SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Athens, Greece, 05/11/2. https://doi.org/10.1109/SIPS.2005.1579833

Efficient design of symbol detector for MIMO-OFDM based wireless LANs. / Seungpyo, Noh; Yunho, Jung; Jaeseok, Kim.
SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation, Proceedings. 2005. p. 25-29 1579833 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Yunho, Jung

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N2 - In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18um CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.

AB - In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18um CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.

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Efficient design of symbol detector for MIMO-OFDM based wireless LANs

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