Efficient BIST scheme for A/D converters

K. Kim, Y. J. Kim, Y. S. Shin, D. Song, S. Kang

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


As SOC and complex systems usually include analogue IPs, it becomes more important to test analogue devices efficiently. The reason for this is that analogue testing for high quality requires substantial testing costs although the analogue portion in a whole chip or in a system is usually very small. In the paper, an efficient low-cost built-in self-test (BIST) scheme is developed for testing A/D converters. The key ideas are to use a triangular wave as a test input signal and to analyse the output response for functional testing. In order to perform functional testing, new fault models called successive value, oscillation and bit faults are proposed. Testing these faults guarantees the quality of A/D converters. For experimental results, a Δ-Σ A/D converter and a pipeline A/D converter are used. The results show that the new BIST scheme is very efficient in terms of fault coverage and hardware overhead.

Original languageEnglish
Pages (from-to)597-604
Number of pages8
JournalIEE Proceedings: Circuits, Devices and Systems
Issue number6
Publication statusPublished - 2005 Dec

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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