Efficient algorithm and architecture for scan conversion in HDTV

M. H. Yang, J. W. Lee, S. Kang

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


The main objective of this paper is to develop an efficient algorithm and architecture for scan conversion in high definition television. Scan conversion requires rapid operations of a large amount of image signal data, thus complex algorithm, architecture, and a large memory are necessary. A simple and effective interpolation method and a pipelined parallel architecture using memory partitioning for the real time operation are proposed. In the new interpolation algorithm, the new image data with edge direction information can be obtained using a simple calculation which considers six neighbouring pixels. To reduce the operation time and memory size, a pipelined parallel architecture is used, and the memory is partitioned into several memory banks. Thus, only small operations with a small memory and short operation time, are for the new algorithm and architecture.

Original languageEnglish
Pages (from-to)287-291
Number of pages5
JournalIEE Proceedings: Computers and Digital Techniques
Issue number4
Publication statusPublished - 1998

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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