We investigate the effects of guard-ring (GR) structures on the performance of silicon avalanche photodetectors (APDs) fabricated with the standard complementary metal-oxide-semiconductor (CMOS) technology. Four types of CMOS-compatible APDs (CMOS-APDs) based on the p +/n-well junction with different GR structures are fabricated, and their electric-field profiles are simulated and analyzed. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth for CMOS-APDs are measured and compared. It is demonstrated that the GR realized with shallow trench isolation provides the best CMOS-APD performance.
|Number of pages||3|
|Journal||IEEE Electron Device Letters|
|Publication status||Published - 2012 Jan|
Bibliographical noteFunding Information:
Manuscript received September 13, 2011; accepted October 7, 2011. Date of publication November 24, 2011; date of current version December 23, 2011. This work was supported by the Mid-career Research Program through an NRF grant funded by MEST (2010-0014798). The review of this letter was arranged by Editor P. K.-L. Yu.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering