Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs

Chang Yong Kang; Ji Woon Yang; Jungwoo Oh; Rino Choi; Young Jun Suh; H. C. Floresca; Jiyoung Kim; Moon Kim; Byoung Hun Lee; Hsing Huang Tseng; Raj Jammy

doi:10.1109/LED.2008.919782

Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs

Chang Yong Kang, Ji Woon Yang, Jungwoo Oh, Rino Choi, Young Jun Suh, H. C. Floresca, Jiyoung Kim, Moon Kim, Byoung Hun Lee, Hsing Huang Tseng, Raj Jammy

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

17 Citations (Scopus)

Abstract

In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-κ silicon-on-insulator fin-shaped field-effect transistors were studied. From a convergent-beam electron-diffraction analysis and simulation study, a 3-nm TiN electrode was found to lead to significantly higher tensile stress on the Si substrate than a 20-nm TiN electrode. This high stress-induced fast bulk carrier generation results in the transient current-time characteristics. Therefore, 3- and 20-nm TiN electrodes are the excellent choice for nMOSFETs and pMOSFETs, respectively, which is from the standpoint of strain engineering, threshold voltage (V_th ), and performance. Due to the metal-induced strain, I_dsat improvements of 15% and 12% for nMOSFETs and pMOSFETs, respectively, were achieved.

Original language	English
Pages (from-to)	487-490
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	29
Issue number	5
DOIs	https://doi.org/10.1109/LED.2008.919782
Publication status	Published - 2008 May

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2008.919782

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Kang, C. Y., Yang, J. W., Oh, J., Choi, R., Suh, Y. J., Floresca, H. C., Kim, J., Kim, M., Lee, B. H., Tseng, H. H., & Jammy, R. (2008). Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs. IEEE Electron Device Letters, 29(5), 487-490. https://doi.org/10.1109/LED.2008.919782

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title = "Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs",

abstract = "In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-κ silicon-on-insulator fin-shaped field-effect transistors were studied. From a convergent-beam electron-diffraction analysis and simulation study, a 3-nm TiN electrode was found to lead to significantly higher tensile stress on the Si substrate than a 20-nm TiN electrode. This high stress-induced fast bulk carrier generation results in the transient current-time characteristics. Therefore, 3- and 20-nm TiN electrodes are the excellent choice for nMOSFETs and pMOSFETs, respectively, which is from the standpoint of strain engineering, threshold voltage (Vth ), and performance. Due to the metal-induced strain, Idsat improvements of 15% and 12% for nMOSFETs and pMOSFETs, respectively, were achieved.",

author = "Kang, {Chang Yong} and Yang, {Ji Woon} and Jungwoo Oh and Rino Choi and Suh, {Young Jun} and Floresca, {H. C.} and Jiyoung Kim and Moon Kim and Lee, {Byoung Hun} and Tseng, {Hsing Huang} and Raj Jammy",

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doi = "10.1109/LED.2008.919782",

language = "English",

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Kang, CY, Yang, JW, Oh, J, Choi, R, Suh, YJ, Floresca, HC, Kim, J, Kim, M, Lee, BH, Tseng, HH & Jammy, R 2008, 'Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs', IEEE Electron Device Letters, vol. 29, no. 5, pp. 487-490. https://doi.org/10.1109/LED.2008.919782

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T1 - Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs

AU - Kang, Chang Yong

AU - Yang, Ji Woon

AU - Oh, Jungwoo

AU - Choi, Rino

AU - Suh, Young Jun

AU - Floresca, H. C.

AU - Kim, Jiyoung

AU - Kim, Moon

AU - Lee, Byoung Hun

AU - Tseng, Hsing Huang

AU - Jammy, Raj

PY - 2008/5

Y1 - 2008/5

N2 - In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-κ silicon-on-insulator fin-shaped field-effect transistors were studied. From a convergent-beam electron-diffraction analysis and simulation study, a 3-nm TiN electrode was found to lead to significantly higher tensile stress on the Si substrate than a 20-nm TiN electrode. This high stress-induced fast bulk carrier generation results in the transient current-time characteristics. Therefore, 3- and 20-nm TiN electrodes are the excellent choice for nMOSFETs and pMOSFETs, respectively, which is from the standpoint of strain engineering, threshold voltage (Vth ), and performance. Due to the metal-induced strain, Idsat improvements of 15% and 12% for nMOSFETs and pMOSFETs, respectively, were achieved.

AB - In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-κ silicon-on-insulator fin-shaped field-effect transistors were studied. From a convergent-beam electron-diffraction analysis and simulation study, a 3-nm TiN electrode was found to lead to significantly higher tensile stress on the Si substrate than a 20-nm TiN electrode. This high stress-induced fast bulk carrier generation results in the transient current-time characteristics. Therefore, 3- and 20-nm TiN electrodes are the excellent choice for nMOSFETs and pMOSFETs, respectively, which is from the standpoint of strain engineering, threshold voltage (Vth ), and performance. Due to the metal-induced strain, Idsat improvements of 15% and 12% for nMOSFETs and pMOSFETs, respectively, were achieved.

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Effects of film stress modulation using TiN metal gate on stress engineering and its impact on device characteristics in metal gate/ high-κ dielectric SOI FinFETs

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