Abstract
In multiprocessor systems, the cache misses due to coherency transactions occupy lots of cache misses. However, this type of cache misses are strongly dependent on the sharing types of shared data among processors, especially, the false sharing. Until now, the small cache block size has been used to avoid the false sharing in many multiprocessor systems. But, the smaller the cache block size, the lower the chance availing of the prefetching effect. Moreover, it is shown that high spatial locality appears in many parallel programs. This paper presents two advanced full-map directory schemes which provide low cache miss ratio and communication traffics by avoiding the false sharing and taking advantage of the spatial locality existing in many parallel programs. The performance was evaluated by the event-driven simulator and the empirical results show that the proposed scheme can provide about 6 to approximately 77% decrease in the cache miss ratio and 46 to approximately 96% decrease in the communication traffics.
Original language | English |
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Pages | 7-11 |
Number of pages | 5 |
Publication status | Published - 1997 |
Event | Proceedings of the 1997 2nd High Performance Computing on the Information Superhighway, HPC Asia'97 - Seoul, South Korea Duration: 1997 Apr 28 → 1997 May 2 |
Other
Other | Proceedings of the 1997 2nd High Performance Computing on the Information Superhighway, HPC Asia'97 |
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City | Seoul, South Korea |
Period | 97/4/28 → 97/5/2 |
All Science Journal Classification (ASJC) codes
- Computer Science(all)