Effective fixed-point pipelined divider for mobile rendering processors

Woo Chan Park; Jun Hyun Bae; Jinhong Park; Tack Don Han; Yong Jin Park

doi:10.1587/transinf.E96.D.1443

Effective fixed-point pipelined divider for mobile rendering processors

Woo Chan Park, Jun Hyun Bae, Jinhong Park, Tack Don Han, Yong Jin Park

College of Computing

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we proposed that an area- and speedeffective fixed-point pipelined divider be used for reducing the bit-width of a division unit to fit a mobile rendering processor. To decide the bit-width of a division unit, error analysis has been carried out in various ways. As a result, when the original bit-width was 31-bit, the proposed method reduced the bit-width to 24-bit and reduced the area by 42% with a maximum error of 0.00001%.

Original language	English
Pages (from-to)	1443-1448
Number of pages	6
Journal	IEICE Transactions on Information and Systems
Volume	E96-D
Issue number	7
DOIs	https://doi.org/10.1587/transinf.E96.D.1443
Publication status	Published - 2013 Jul

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Computer Vision and Pattern Recognition
Electrical and Electronic Engineering
Artificial Intelligence

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10.1587/transinf.E96.D.1443

Cite this

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Effective fixed-point pipelined divider for mobile rendering processors

Abstract

All Science Journal Classification (ASJC) codes

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