Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

Heedo Na; Jinho Oh; Kyumin Lee; Jonggi Kim; Sunghoon Lee; Dong Hyeok Lim; Mann Ho Cho; Hyunchul Sohn

doi:10.1016/j.mee.2013.04.025

Effect of SiO₂ tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

Heedo Na, Jinho Oh, Kyumin Lee, Jonggi Kim, Sunghoon Lee, Dong Hyeok Lim, Mann Ho Cho, Hyunchul Sohn

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

In this study, we investigated the effect of various SiO₂ tunnel layers on the characteristics of charge trap memories with Metal/SiO ₂/Si₃N₄/SiO₂/n-type poly-Si (MONOS) structures. For MONOS devices, SiO₂ tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO₂ tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO₂ and LP-TEOS SiO₂ showed larger breakdown voltages with more uniform thickness than thermal SiO₂ on poly-Si channels. MONOS devices with radical SiO₂ and LP-TEOS SiO₂ tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO ₂. In particular, the MONOS device with LP-TEOS SiO₂ showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO₂. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO₂ tunnel dielectrics.

Original language	English
Pages (from-to)	6-11
Number of pages	6
Journal	Microelectronic Engineering
Volume	110
DOIs	https://doi.org/10.1016/j.mee.2013.04.025
Publication status	Published - 2013

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

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10.1016/j.mee.2013.04.025

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title = "Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels",

abstract = "In this study, we investigated the effect of various SiO2 tunnel layers on the characteristics of charge trap memories with Metal/SiO 2/Si3N4/SiO2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO2 and LP-TEOS SiO2 showed larger breakdown voltages with more uniform thickness than thermal SiO2 on poly-Si channels. MONOS devices with radical SiO2 and LP-TEOS SiO2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO 2. In particular, the MONOS device with LP-TEOS SiO2 showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO2 tunnel dielectrics.",

author = "Heedo Na and Jinho Oh and Kyumin Lee and Jonggi Kim and Sunghoon Lee and Lim, {Dong Hyeok} and Cho, {Mann Ho} and Hyunchul Sohn",

year = "2013",

doi = "10.1016/j.mee.2013.04.025",

language = "English",

volume = "110",

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journal = "Microelectronic Engineering",

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T1 - Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

AU - Na, Heedo

AU - Oh, Jinho

AU - Lee, Kyumin

AU - Kim, Jonggi

AU - Lee, Sunghoon

AU - Lim, Dong Hyeok

AU - Cho, Mann Ho

AU - Sohn, Hyunchul

PY - 2013

Y1 - 2013

N2 - In this study, we investigated the effect of various SiO2 tunnel layers on the characteristics of charge trap memories with Metal/SiO 2/Si3N4/SiO2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO2 and LP-TEOS SiO2 showed larger breakdown voltages with more uniform thickness than thermal SiO2 on poly-Si channels. MONOS devices with radical SiO2 and LP-TEOS SiO2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO 2. In particular, the MONOS device with LP-TEOS SiO2 showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO2 tunnel dielectrics.

AB - In this study, we investigated the effect of various SiO2 tunnel layers on the characteristics of charge trap memories with Metal/SiO 2/Si3N4/SiO2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO2 and LP-TEOS SiO2 showed larger breakdown voltages with more uniform thickness than thermal SiO2 on poly-Si channels. MONOS devices with radical SiO2 and LP-TEOS SiO2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO 2. In particular, the MONOS device with LP-TEOS SiO2 showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO2 tunnel dielectrics.

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Effect of SiO₂ tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

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