Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test

Hyunggoy Oh; Heetae Kim; Sangjun Lee; Sungho Kang

doi:10.1109/ISOCC.2018.8649911

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test

Hyunggoy Oh, Heetae Kim, Sangjun Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2018, ISOCC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	7-8
Number of pages	2
ISBN (Electronic)	9781538679609
DOIs	https://doi.org/10.1109/ISOCC.2018.8649911
Publication status	Published - 2019 Feb 22
Event	15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of Duration: 2018 Nov 12 → 2018 Nov 15

Publication series

Name	Proceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference	15th International SoC Design Conference, ISOCC 2018
Country/Territory	Korea, Republic of
City	Daegu
Period	18/11/12 → 18/11/15

Bibliographical note

Funding Information:
This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISOCC.2018.8649911

Cite this

Oh, H., Kim, H., Lee, S., & Kang, S. (2019). Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 7-8). Article 8649911 (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649911

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abstract = "The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.",

author = "Hyunggoy Oh and Heetae Kim and Sangjun Lee and Sungho Kang",

note = "Funding Information: This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC]. Publisher Copyright: {\textcopyright} 2018 IEEE.; 15th International SoC Design Conference, ISOCC 2018 ; Conference date: 12-11-2018 Through 15-11-2018",

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Oh, H, Kim, H, Lee, S & Kang, S 2019, Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649911, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 7-8, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649911

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. / Oh, Hyunggoy; Kim, Heetae; Lee, Sangjun et al.
Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 7-8 8649911 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC]. Publisher Copyright: © 2018 IEEE.

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N2 - The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.

AB - The NTV circuit has been introduced as a new low power design concept, which increases energy efficiency significantly. However, delay sensitivity of the NTV circuit is a major challenge. In addition, this problem can be more critical during at-speed scan test because of the dynamic voltage drop issue. In this paper, we propose a comparison of dynamic voltage drop induced path delay between STV and NTV circuits during at-speed scan test. To the best knowledge of the authors, it is the first time to analyze the voltage drop induced path delay during the NTV circuit scan test. Experimental results show that the path delay increment of NTV is larger than that of STV although the dynamic voltage drop of NTV is smaller than that of STV.

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Oh H, Kim H, Lee S, Kang S. Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. In Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 7-8. 8649911. (Proceedings - International SoC Design Conference 2018, ISOCC 2018). doi: 10.1109/ISOCC.2018.8649911

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test

Abstract

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UN SDGs

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