Dynamic power management of DRAM using accessed physical addresses

Jung Hi Min, Hojung Cha, Vason P. Srini

Research output: Contribution to journalArticlepeer-review


Power management is an important part of handheld systems such as PDAs, smartphones, and other battery operated digital devices. A handheld system can transition the nodes of a DRAM to low power state to reduce energy consumption. We propose an efficient method for dynamic power management (DPM) of DRAM based on accessed physical addresses. The proposed method also reduces the number of times resynchronization is done. There is no need to collect scattered pages, as in conventional page clustering mechanisms that focus on virtual memory (VM). Simulation result shows that the proposed method reduces Energy * Delay Product by as much as 75% when compared to DRAMs with no DPM.

Original languageEnglish
Pages (from-to)15-24
Number of pages10
JournalMicroprocessors and Microsystems
Issue number1
Publication statusPublished - 2007 Feb 12

Bibliographical note

Funding Information:
This work was supported in part by the National Research Laboratory (NRL) program of the Korea Science and Engineering Foundation (2005-01352), the ITRC programs (MMRC) of IITA, Korea, and the Seoul R&BD Program of City of Seoul, Korea.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence


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