Discussion of cost-effective redundancy architectures

Keewon Cho; Jooyoung Kim; Hayoung Lee; Sungho Kang

doi:10.1109/ISOCC.2016.7799751

Discussion of cost-effective redundancy architectures

Keewon Cho, Jooyoung Kim, Hayoung Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

To get a reasonable yield, memories incorporate redundancies to substitute for faulty cells. As the performance of repair algorithm reaches some saturation point, recent studies focus on various redundancy architectures for higher repair rate. In this paper, three kinds of spares, i.e., local, common, and global spares, are discussed to analyze the efficiency of redundancy architectures in respect of the repair cost. In order to estimate the impact of each spare, more than a hundred redundancy architectures are simulated with different faulty patterns. This paper performs a data analysis and suggests cost-effective redundancy architectures.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference
Subtitle of host publication	Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	97-98
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799751
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Publication series

Name	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799751

Cite this

Cho, K., Kim, J., Lee, H., & Kang, S. (2016). Discussion of cost-effective redundancy architectures. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 97-98). [7799751] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799751

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title = "Discussion of cost-effective redundancy architectures",

abstract = "To get a reasonable yield, memories incorporate redundancies to substitute for faulty cells. As the performance of repair algorithm reaches some saturation point, recent studies focus on various redundancy architectures for higher repair rate. In this paper, three kinds of spares, i.e., local, common, and global spares, are discussed to analyze the efficiency of redundancy architectures in respect of the repair cost. In order to estimate the impact of each spare, more than a hundred redundancy architectures are simulated with different faulty patterns. This paper performs a data analysis and suggests cost-effective redundancy architectures.",

author = "Keewon Cho and Jooyoung Kim and Hayoung Lee and Sungho Kang",

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doi = "10.1109/ISOCC.2016.7799751",

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series = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",

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Cho, K, Kim, J, Lee, H & Kang, S 2016, Discussion of cost-effective redundancy architectures. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799751, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things, Institute of Electrical and Electronics Engineers Inc., pp. 97-98, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799751

Discussion of cost-effective redundancy architectures. / Cho, Keewon; Kim, Jooyoung; Lee, Hayoung et al.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 97-98 7799751 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - To get a reasonable yield, memories incorporate redundancies to substitute for faulty cells. As the performance of repair algorithm reaches some saturation point, recent studies focus on various redundancy architectures for higher repair rate. In this paper, three kinds of spares, i.e., local, common, and global spares, are discussed to analyze the efficiency of redundancy architectures in respect of the repair cost. In order to estimate the impact of each spare, more than a hundred redundancy architectures are simulated with different faulty patterns. This paper performs a data analysis and suggests cost-effective redundancy architectures.

AB - To get a reasonable yield, memories incorporate redundancies to substitute for faulty cells. As the performance of repair algorithm reaches some saturation point, recent studies focus on various redundancy architectures for higher repair rate. In this paper, three kinds of spares, i.e., local, common, and global spares, are discussed to analyze the efficiency of redundancy architectures in respect of the repair cost. In order to estimate the impact of each spare, more than a hundred redundancy architectures are simulated with different faulty patterns. This paper performs a data analysis and suggests cost-effective redundancy architectures.

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Discussion of cost-effective redundancy architectures

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