Discussion of cost-effective redundancy architectures

Keewon Cho, Jooyoung Kim, Hayoung Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


To get a reasonable yield, memories incorporate redundancies to substitute for faulty cells. As the performance of repair algorithm reaches some saturation point, recent studies focus on various redundancy architectures for higher repair rate. In this paper, three kinds of spares, i.e., local, common, and global spares, are discussed to analyze the efficiency of redundancy architectures in respect of the repair cost. In order to estimate the impact of each spare, more than a hundred redundancy architectures are simulated with different faulty patterns. This paper performs a data analysis and suggests cost-effective redundancy architectures.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467393089
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things


Other13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation


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