Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector

Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


This article presents design techniques for a PAM-4 baud-rate digital clock and data recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate phase detector (PD) is designed in an inductive and stochastic way, so there is a clear difference from the existing deductive and logical method used in sign-sign Mueller-Müller PD (SS-MMPD), a representative baud-rate PD. By collecting the histograms of the sequential PAM-4 patterns under EARLY and LATE sampling phases and calculating optimal weights, the SPD exhibits optimized phase-locking characteristic that maximizes the PAM-4 vertical eye opening (VEO) compared with the conventional logical approaches. In addition, unlike SS-MMPD, which may suffer from a severe multiple-locking problem, the SPD tracks a unique and optimal sampling phase even with an adaptive decision-feedback equalizer (DFE). For verification, a prototype PAM-4 receiver is fabricated in 40-nm CMOS technology and occupies 0.24 mm2. Tested with PRBS-7 patterns, it achieves a bit error rate (BER) of less than 10-11 and energy efficiency of 2.4 pJ/b at 48 Gb/s.

Original languageEnglish
Pages (from-to)3014-3024
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number10
Publication statusPublished - 2022 Oct 1

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector'. Together they form a unique fingerprint.

Cite this