Design Guidelines of Hafnia Ferroelectrics and Gate-Stack for Multilevel-Cell FeFET

In this work, we demonstrate a novel approach to superior multilevel-cell (MLC) ferroelectric field-effect transistor (FeFET) with a large memory window (MW) and negligible VT variation toward MLC operation. We realized high ferroelectricity in a relatively thick HZO ferroelectric (FE) layer for FeFET with a large MW [MW thickness of FE layer (TFE)] based on our understanding of thermodynamics and kinetics. Moreover, we employed the MFMIS gate-stack with a floating gate for FeFET to minimize the VT variation with respect to different distributions of phase and grain size. We applied experimentally obtained materials and electrical data from HZO to TCAD simulation to statistically analyze the impact of materials and gate-stack on the MW and the VT variation of FeFET. Consequently, we found that increasing the Zr content of HZO effectively reduces the VT variation while significantly enhancing the MW. Also, compared to conventional metal FEs insulator silicon (MFIS) FeFET, the (metal FEs metal insulator silicon) MFMIS FeFET shows significantly reduced VT variation and an enlarged MW by inducing uniform channel conductivity due to the equalization effect of the inserted floating gate even for the spatial distribution of FE grains in the HZO layer. Our experimental and simulation methodologies covering materials engineering and gate-stack provide a visible solution for the design of future FeFETs with outstanding MLC operation.