Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs

Gaurav Kaushal; K. Subramanyam; Siva Nageswar Rao; G. Vidya; Radhika Ramya; Sadulla Shaik; H. Jeong; S. O. Jung; Ramesh Vaddi

doi:10.1109/ISOCC.2014.7087570

Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs

Gaurav Kaushal
, K. Subramanyam
, Siva Nageswar Rao
, G. Vidya
, Radhika Ramya
, Sadulla Shaik
, H. Jeong
, S. O. Jung
, Ramesh Vaddi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large I_on/I_off etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, g_m/I_ds, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.

Original language	English
Title of host publication	ISOCC 2014 - International SoC Design Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	32-33
Number of pages	2
ISBN (Electronic)	9781479951260
DOIs	https://doi.org/10.1109/ISOCC.2014.7087570
Publication status	Published - 2015 Apr 16
Event	11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of Duration: 2014 Nov 3 → 2014 Nov 6

Publication series

Name	ISOCC 2014 - International SoC Design Conference

Other

Other	11th International SoC Design Conference, ISOCC 2014
Country/Territory	Korea, Republic of
City	Jeju
Period	14/11/3 → 14/11/6

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Hardware and Architecture

Access to Document

10.1109/ISOCC.2014.7087570

Cite this

Kaushal, G., Subramanyam, K., Rao, S. N., Vidya, G., Ramya, R., Shaik, S., Jeong, H., Jung, S. O., & Vaddi, R. (2015). Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. In ISOCC 2014 - International SoC Design Conference (pp. 32-33). Article 7087570 (ISOCC 2014 - International SoC Design Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2014.7087570

Kaushal, Gaurav ; Subramanyam, K. ; Rao, Siva Nageswar et al. / Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 32-33 (ISOCC 2014 - International SoC Design Conference).

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title = "Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs",

abstract = "This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.",

author = "Gaurav Kaushal and K. Subramanyam and Rao, \{Siva Nageswar\} and G. Vidya and Radhika Ramya and Sadulla Shaik and H. Jeong and Jung, \{S. O.\} and Ramesh Vaddi",

year = "2015",

month = apr,

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doi = "10.1109/ISOCC.2014.7087570",

language = "English",

series = "ISOCC 2014 - International SoC Design Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "11th International SoC Design Conference, ISOCC 2014 ; Conference date: 03-11-2014 Through 06-11-2014",

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Kaushal, G, Subramanyam, K, Rao, SN, Vidya, G, Ramya, R, Shaik, S, Jeong, H, Jung, SO & Vaddi, R 2015, Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. in ISOCC 2014 - International SoC Design Conference., 7087570, ISOCC 2014 - International SoC Design Conference, Institute of Electrical and Electronics Engineers Inc., pp. 32-33, 11th International SoC Design Conference, ISOCC 2014, Jeju, Korea, Republic of, 14/11/3. https://doi.org/10.1109/ISOCC.2014.7087570

Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. / Kaushal, Gaurav; Subramanyam, K.; Rao, Siva Nageswar et al.
ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 32-33 7087570 (ISOCC 2014 - International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Kaushal, Gaurav

AU - Subramanyam, K.

AU - Rao, Siva Nageswar

AU - Vidya, G.

AU - Ramya, Radhika

AU - Shaik, Sadulla

AU - Jeong, H.

AU - Jung, S. O.

AU - Vaddi, Ramesh

PY - 2015/4/16

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N2 - This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.

AB - This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.

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M3 - Conference contribution

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BT - ISOCC 2014 - International SoC Design Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th International SoC Design Conference, ISOCC 2014

Y2 - 3 November 2014 through 6 November 2014

ER -

Kaushal G, Subramanyam K, Rao SN, Vidya G, Ramya R, Shaik S et al. Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs. In ISOCC 2014 - International SoC Design Conference. Institute of Electrical and Electronics Engineers Inc. 2015. p. 32-33. 7087570. (ISOCC 2014 - International SoC Design Conference). doi: 10.1109/ISOCC.2014.7087570

Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs

Abstract

Publication series

Other

UN SDGs

All Science Journal Classification (ASJC) codes

Access to Document

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Cite this