TY - GEN
T1 - Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs
AU - Kaushal, Gaurav
AU - Subramanyam, K.
AU - Rao, Siva Nageswar
AU - Vidya, G.
AU - Ramya, Radhika
AU - Shaik, Sadulla
AU - Jeong, H.
AU - Jung, S. O.
AU - Vaddi, Ramesh
PY - 2015/4/16
Y1 - 2015/4/16
N2 - This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.
AB - This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large Ion/Ioff etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, gm/Ids, BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.
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U2 - 10.1109/ISOCC.2014.7087570
DO - 10.1109/ISOCC.2014.7087570
M3 - Conference contribution
T3 - ISOCC 2014 - International SoC Design Conference
SP - 32
EP - 33
BT - ISOCC 2014 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th International SoC Design Conference, ISOCC 2014
Y2 - 3 November 2014 through 6 November 2014
ER -
