Design and implementation of MIMO-OFDM baseband processor for high-speed wireless LANs

Yunho Jung; Jiho Kim; Seongjoo Lee; Hongil Yoon; Jaeseok Kim

doi:10.1109/TCSII.2007.895330

Design and implementation of MIMO-OFDM baseband processor for high-speed wireless LANs

Yunho Jung, Jiho Kim, Seongjoo Lee, Hongil Yoon, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

37 Citations (Scopus)

Abstract

In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm² using 0.18-μm CMOS process.

Original language	English
Pages (from-to)	631-635
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	54
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2007.895330
Publication status	Published - 2007 Jul 7

Bibliographical note

Funding Information:
Manuscript received December 5, 2006; revised February 3, 2007. This work was supported by the Ministry of Information and Communication (MIC), Korea, under the Information Technology Research Center (ITRC) support program supervised by the Institute of Information Technology Assessment (IITA). This paper was recommended by Associate Editor B. Nikolic.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2007.895330

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title = "Design and implementation of MIMO-OFDM baseband processor for high-speed wireless LANs",

abstract = "In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm2 using 0.18-μm CMOS process.",

keywords = "Multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM), space division multiplexed OFDM (SDM-OFDM), space-frequency block coded OFDM (SFBC-OFDM), wireless LANs (WLANs)",

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note = "Funding Information: Manuscript received December 5, 2006; revised February 3, 2007. This work was supported by the Ministry of Information and Communication (MIC), Korea, under the Information Technology Research Center (ITRC) support program supervised by the Institute of Information Technology Assessment (IITA). This paper was recommended by Associate Editor B. Nikolic.",

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AU - Lee, Seongjoo

AU - Yoon, Hongil

AU - Kim, Jaeseok

N1 - Funding Information: Manuscript received December 5, 2006; revised February 3, 2007. This work was supported by the Ministry of Information and Communication (MIC), Korea, under the Information Technology Research Center (ITRC) support program supervised by the Institute of Information Technology Assessment (IITA). This paper was recommended by Associate Editor B. Nikolic.

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N2 - In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm2 using 0.18-μm CMOS process.

AB - In this brief, we present the design and implementation results of a digital 120 Mb/s multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) wireless LAN (WLAN) baseband processor based on the proposed decoding algorithms. The processor has two MIMO-OFDM modes, space-frequency block coded OFDM and space division multiplexed OFDM. From those, it achieves a considerable performance gain as well as supports double data rates compared to the conventional IEEE 802.11a WLANs. In the results of performance evaluation, the processor requires a signal-to-noise ratio of 1.8-27 dB for transmission modes at 10% packet error rate, and the chip is implemented with 4.8 M transistors in 3.9 ×3.9 mm2 using 0.18-μm CMOS process.

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KW - space-frequency block coded OFDM (SFBC-OFDM)

KW - wireless LANs (WLANs)

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Design and implementation of MIMO-OFDM baseband processor for high-speed wireless LANs

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