Design and effectiveness of small-sized decoupled dispatch queues

Won W. Ro, Jean Luc Gaudiot

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues in modern superscalar microprocessors. However, such large queues are inevitably accompanied by high circuit complexity which correspondingly limits the pipeline clock rates. This is due to the fact that most of today's designs are based upon a centralized dispatch queue which depends on globally broadcasting operations to wake up and select the ready instructions. As an alternative to this conventional design, we propose the design of hierarchically distributed dispatch queues, based on the access/execute decoupled architecture model. Simulation results based on 14 data intensive benchmarks show that our DDQ (Decoupled Dispatch Queues) design achieves performance comparable to a superscalar machine with a large dispatch queue. We also show that our DDQ can be designed with small-sized, distributed dispatch queues which consequently can be implemented with low hardware complexity and high clock rates.

Original languageEnglish
Title of host publicationEuro-Par 2006 Parallel Processing - 12th International Euro-Par Conference, Proceedings
PublisherSpringer Verlag
Number of pages10
ISBN (Print)3540377832, 9783540377832
Publication statusPublished - 2006
Event12th International Euro-Par Conference 2006 - Lisbon, Portugal
Duration: 2006 Aug 282006 Sept 1

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4128 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other12th International Euro-Par Conference 2006

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)


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