Demonstration of Lg ∼ nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high Ion/Ioff (>5 × 104, and controlled short channel effects (SCEs)

Se Hoon Lee; Prashant Majhi; Jungwoo Oh; Barry Sassman; Chadwin Young; Anupama Bowonder; Wei Yip Loh; Kyu Jin Choi; Byung Jin Cho; Hi Deok Lee; Paul Kirsch; Harlan Rusty Harris; Wilman Tsai; Suman Datta; Hsing Huang Tseng; Sanjay K. Banerjee; Raj Jammy

doi:10.1109/LED.2008.2002073

Demonstration of L_g ∼ nm pMOSFETs with Si/Si_0.25Ge_0.75/Si channels, high I_on/I_off (>5 × 10⁴, and controlled short channel effects (SCEs)

Se Hoon Lee, Prashant Majhi, Jungwoo Oh, Barry Sassman, Chadwin Young, Anupama Bowonder, Wei Yip Loh, Kyu Jin Choi, Byung Jin Cho, Hi Deok Lee, Paul Kirsch, Harlan Rusty Harris, Wilman Tsai, Suman Datta, Hsing Huang Tseng, Sanjay K. Banerjee, Raj Jammy

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

21 Citations (Scopus)

Abstract

High-performance sub-60 nm Si/SiGe (Ge: ∼ 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high- κ/metal gate stacks with ∼1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length L_g devices demonstrate not only controlled short channel effects, but also an excellent on-off current (I_on /I_oof ratio (∼5 × 10⁴ at 55-nm L_g. The intrinsic gate delay of these heterostructures is ∼3 ps at I_on/I_off ∼ 10⁴ OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short L_f devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

Original language	English
Pages (from-to)	1017-1020
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	29
Issue number	9
DOIs	https://doi.org/10.1109/LED.2008.2002073
Publication status	Published - 2008

Bibliographical note

Funding Information:
Manuscript received April 10, 2008; revised June 7, 2008. This work was supported in part by Department of Energy and in part by the Defense Advanced Research Projects Agency. The review of this letter was arranged by Editor M. Östling.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2008.2002073

Cite this

Lee, S. H., Majhi, P., Oh, J., Sassman, B., Young, C., Bowonder, A., Loh, W. Y., Choi, K. J., Cho, B. J., Lee, H. D., Kirsch, P., Harris, H. R., Tsai, W., Datta, S., Tseng, H. H., Banerjee, S. K., & Jammy, R. (2008). Demonstration of L_g ∼ nm pMOSFETs with Si/Si_0.25Ge_0.75/Si channels, high I_on/I_off (>5 × 10⁴, and controlled short channel effects (SCEs). IEEE Electron Device Letters, 29(9), 1017-1020. https://doi.org/10.1109/LED.2008.2002073

@article{7167172b471a4857930745ada5e47571,

title = "Demonstration of Lg ∼ nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high Ion/Ioff (>5 × 104, and controlled short channel effects (SCEs)",

abstract = "High-performance sub-60 nm Si/SiGe (Ge: ∼ 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high- κ/metal gate stacks with ∼1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length Lg devices demonstrate not only controlled short channel effects, but also an excellent on-off current (Ion /Ioof ratio (∼5 × 104 at 55-nm Lg. The intrinsic gate delay of these heterostructures is ∼3 ps at Ion/Ioff ∼ 104 OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short Lf devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.",

author = "Lee, {Se Hoon} and Prashant Majhi and Jungwoo Oh and Barry Sassman and Chadwin Young and Anupama Bowonder and Loh, {Wei Yip} and Choi, {Kyu Jin} and Cho, {Byung Jin} and Lee, {Hi Deok} and Paul Kirsch and Harris, {Harlan Rusty} and Wilman Tsai and Suman Datta and Tseng, {Hsing Huang} and Banerjee, {Sanjay K.} and Raj Jammy",

note = "Funding Information: Manuscript received April 10, 2008; revised June 7, 2008. This work was supported in part by Department of Energy and in part by the Defense Advanced Research Projects Agency. The review of this letter was arranged by Editor M. {\"O}stling.",

year = "2008",

doi = "10.1109/LED.2008.2002073",

language = "English",

volume = "29",

pages = "1017--1020",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

Lee, SH, Majhi, P, Oh, J, Sassman, B, Young, C, Bowonder, A, Loh, WY, Choi, KJ, Cho, BJ, Lee, HD, Kirsch, P, Harris, HR, Tsai, W, Datta, S, Tseng, HH, Banerjee, SK & Jammy, R 2008, 'Demonstration of L_g ∼ nm pMOSFETs with Si/Si_0.25Ge_0.75/Si channels, high I_on/I_off (>5 × 10⁴, and controlled short channel effects (SCEs)', IEEE Electron Device Letters, vol. 29, no. 9, pp. 1017-1020. https://doi.org/10.1109/LED.2008.2002073

TY - JOUR

T1 - Demonstration of Lg ∼ nm pMOSFETs with Si/Si0.25Ge0.75/Si channels, high Ion/Ioff (>5 × 104, and controlled short channel effects (SCEs)

AU - Lee, Se Hoon

AU - Majhi, Prashant

AU - Oh, Jungwoo

AU - Sassman, Barry

AU - Young, Chadwin

AU - Bowonder, Anupama

AU - Loh, Wei Yip

AU - Choi, Kyu Jin

AU - Cho, Byung Jin

AU - Lee, Hi Deok

AU - Kirsch, Paul

AU - Harris, Harlan Rusty

AU - Tsai, Wilman

AU - Datta, Suman

AU - Tseng, Hsing Huang

AU - Banerjee, Sanjay K.

AU - Jammy, Raj

N1 - Funding Information: Manuscript received April 10, 2008; revised June 7, 2008. This work was supported in part by Department of Energy and in part by the Defense Advanced Research Projects Agency. The review of this letter was arranged by Editor M. Östling.

PY - 2008

Y1 - 2008

N2 - High-performance sub-60 nm Si/SiGe (Ge: ∼ 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high- κ/metal gate stacks with ∼1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length Lg devices demonstrate not only controlled short channel effects, but also an excellent on-off current (Ion /Ioof ratio (∼5 × 104 at 55-nm Lg. The intrinsic gate delay of these heterostructures is ∼3 ps at Ion/Ioff ∼ 104 OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short Lf devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

AB - High-performance sub-60 nm Si/SiGe (Ge: ∼ 75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high- κ/metal gate stacks with ∼1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length Lg devices demonstrate not only controlled short channel effects, but also an excellent on-off current (Ion /Ioof ratio (∼5 × 104 at 55-nm Lg. The intrinsic gate delay of these heterostructures is ∼3 ps at Ion/Ioff ∼ 104 OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short Lf devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

UR - http://www.scopus.com/inward/record.url?scp=50649109671&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50649109671&partnerID=8YFLogxK

U2 - 10.1109/LED.2008.2002073

DO - 10.1109/LED.2008.2002073

M3 - Article

AN - SCOPUS:50649109671

SN - 0741-3106

VL - 29

SP - 1017

EP - 1020

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 9

ER -