Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

K. W. Kim, S. O. Jung, P. Saxena, C. L. Liu, S. M. Kang

Research output: Contribution to journalConference articlepeer-review


Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicron CMOS technology. Often coupling delay is strongly dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual Vt technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low Vt is applied properly.

Original languageEnglish
Pages (from-to)732-737
Number of pages6
JournalProceedings - Design Automation Conference
Publication statusPublished - 2001
Event38th Design Automation Conference - Las Vegas, NV, United States
Duration: 2001 Jun 182001 Jun 22

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering


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