Coupling-aware minimum delay optimisation for domino logic circuits

K. W. Kim, S. O. Jung, T. Kim, S. M. Kang

Research output: Contribution to journalArticlepeer-review


Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organisation or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the minimum-delay path failure through coupling-induced speedup. To tackle the minimum-delay problem for domino logic, we propose a minimum-delay optimisation algorithm considering coupling effects. Experimental results indicate that our algorithm yields a significant increase of minimum-delay without incurring maximum-delay violation.

Original languageEnglish
Pages (from-to)813-814
Number of pages2
JournalElectronics Letters
Issue number13
Publication statusPublished - 2001 Jun 21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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