Abstract
To expose hidden parallelism from programs with complex dependences, modern compilers employ memory profilers to augment imprecise static analyses. Since dynamic dependence patterns among instructions can vary widely depending on the context, such as function call site stack and loop nest level, context-aware memory profiling is of great value for precise memory profiling. However, recording memory dependences with full context information causes huge overheads in terms of CPU cycles and memory space. Existing profilers mitigate this problem by compromising precision, coverage, or both. This paper proposes a new precise Context-Aware Memory Profiling (CAMP) framework that efficiently traces all the memory dependences with full context information. CAMP statically analyzes a context tree of a program that illustrates all the possible dynamic contexts, and simplifies context management during profiling. For 14 programs from SPEC CINT2000 and CINT2006 benchmark suites, CAMP increases speculative parallelism opportunities by 12.6% on average and by up to 63.0% compared to the baseline context-oblivious, loop-aware memory profiler.
Original language | English |
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Title of host publication | Proceedings - 24th IEEE International Conference on High Performance Computing, HiPC 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 328-337 |
Number of pages | 10 |
ISBN (Electronic) | 9781538622933 |
DOIs | |
Publication status | Published - 2018 Feb 7 |
Event | 24th IEEE International Conference on High Performance Computing, HiPC 2017 - Jaipur, India Duration: 2017 Dec 18 → 2017 Dec 21 |
Publication series
Name | Proceedings - 24th IEEE International Conference on High Performance Computing, HiPC 2017 |
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Volume | 2017-December |
Other
Other | 24th IEEE International Conference on High Performance Computing, HiPC 2017 |
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Country/Territory | India |
City | Jaipur |
Period | 17/12/18 → 17/12/21 |
Bibliographical note
Funding Information:We thank the anonymous reviewers for their insightful comments and suggestions. This work is supported by Korea Institute of Science and Technology Information (KISTI) under the grant No.K-16-L01-C03-S03, and the Korean Government (MSIT) under the "Next-Generation Information Computing Development Program" (NRF-2015M3C4A7065646), the "Basic Science Research Program" (NRF-2017R1C1B3009332), the "ICT ConsiUence Creative Program" (IITP-2017-R0346-16-1007), and the "PF Class Heterogeneous High Performance Computer Development" (NRF-2016M3C4A7952587).
Publisher Copyright:
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Hardware and Architecture
- Modelling and Simulation