Computing-In-Memory Using 1T1C Embedded DRAM Cell with Micro Sense Amplifier for Enhancing Throughput

The proposed 1T1C embedded DRAM (eDRAM) based compute-in-memory (CIM) architecture resolves Von-Neumann memory-bottleneck issue that degrades energy consumption and performance in processing neural networks. The proposed CIM architecture uses 1T1C eDRAM cell for better memory density compared to other eDRAM cells (e.g., 2T1C, 3T1C, 4T2C) based CIM architectures. However, the conventional 1T1C eDRAM cell based CIM architecture can only access a single row, unlike other eDRAM cell based CIM architectures because of the destructive read issue. The single-row access causes degradation of throughput. To overcome the limitation of single-row access, the conventional micro sense amplifier (uSA) is considered. However, the conventional uSA is suffered from the short circuit current during the MAC operation. Thus, the MAC operation results can be contaminated. To resolve the short circuit current issue, a newly designed uSA is proposed. The proposed uSA disconnects LBL to prevent uSA from affecting MAC operation results. By using the proposed uSA in every LBL, the proposed 1T1 C eDRAM cell based CIM architecture accesses multiple rows in one column. As a result, the throughput of the proposed 1T1C eDRAM cell based CIM architecture is improved by 5.44X compared to the conventional 1T1C eDRAM cell based CIM architecture.