Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

C. Y. Kang; R. H. Baek; T. W. Kim; D. Ko; D. H. Kim; T. Michalak; C. Borst; D. Veksler; G. Bersuker; R. Hill; C. Hobbs; P. D. Kirsch

doi:10.1109/IEDM.2013.6724566

Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

C. Y. Kang, R. H. Baek, T. W. Kim, D. Ko, D. H. Kim, T. Michalak, C. Borst, D. Veksler, G. Bersuker, R. Hill, C. Hobbs, P. D. Kirsch

Department of Materials Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In this work we present III-V device performance and its variability under various design and process parameters, as compared to Si devices, using MC simulation. III-V device compact/BSIM models are developed, including geometry-dependent parasitic RC. Compared to its Si counterpart, III-V devices exhibit superior performance in I_on, ring oscillator delay (t _pd) and SRAM read time (t_read). We calculated the N _it target for mitigating increments of I_off and subthreshold slopes. For both Si and III-V sub-7nm technology optimization, we propose a direction for technology design to improve performance and area scaling without variability penalty.

Original language	English
Title of host publication	2013 IEEE International Electron Devices Meeting, IEDM 2013
Pages	5.3.1-5.3.4
DOIs	https://doi.org/10.1109/IEDM.2013.6724566
Publication status	Published - 2013
Event	2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States Duration: 2013 Dec 9 → 2013 Dec 11

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2013 IEEE International Electron Devices Meeting, IEDM 2013
Country/Territory	United States
City	Washington, DC
Period	13/12/9 → 13/12/11

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2013.6724566

Cite this

Kang, C. Y., Baek, R. H., Kim, T. W., Ko, D., Kim, D. H., Michalak, T., Borst, C., Veksler, D., Bersuker, G., Hill, R., Hobbs, C., & Kirsch, P. D. (2013). Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 (pp. 5.3.1-5.3.4). Article 6724566 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724566

@inproceedings{de8ffdd3a70f48b3b753e881af64ceff,

title = "Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node",

abstract = "In this work we present III-V device performance and its variability under various design and process parameters, as compared to Si devices, using MC simulation. III-V device compact/BSIM models are developed, including geometry-dependent parasitic RC. Compared to its Si counterpart, III-V devices exhibit superior performance in Ion, ring oscillator delay (t pd) and SRAM read time (tread). We calculated the N it target for mitigating increments of Ioff and subthreshold slopes. For both Si and III-V sub-7nm technology optimization, we propose a direction for technology design to improve performance and area scaling without variability penalty.",

author = "Kang, {C. Y.} and Baek, {R. H.} and Kim, {T. W.} and D. Ko and Kim, {D. H.} and T. Michalak and C. Borst and D. Veksler and G. Bersuker and R. Hill and C. Hobbs and Kirsch, {P. D.}",

year = "2013",

doi = "10.1109/IEDM.2013.6724566",

language = "English",

isbn = "9781479923076",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "5.3.1--5.3.4",

booktitle = "2013 IEEE International Electron Devices Meeting, IEDM 2013",

note = "2013 IEEE International Electron Devices Meeting, IEDM 2013 ; Conference date: 09-12-2013 Through 11-12-2013",

}

Kang, CY, Baek, RH, Kim, TW, Ko, D, Kim, DH, Michalak, T, Borst, C, Veksler, D, Bersuker, G, Hill, R, Hobbs, C & Kirsch, PD 2013, Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node. in 2013 IEEE International Electron Devices Meeting, IEDM 2013., 6724566, Technical Digest - International Electron Devices Meeting, IEDM, pp. 5.3.1-5.3.4, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 13/12/9. https://doi.org/10.1109/IEDM.2013.6724566

Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node. / Kang, C. Y.; Baek, R. H.; Kim, T. W. et al.
2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. p. 5.3.1-5.3.4 6724566 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

AU - Kang, C. Y.

AU - Baek, R. H.

AU - Kim, T. W.

AU - Ko, D.

AU - Kim, D. H.

AU - Michalak, T.

AU - Borst, C.

AU - Veksler, D.

AU - Bersuker, G.

AU - Hill, R.

AU - Hobbs, C.

AU - Kirsch, P. D.

PY - 2013

Y1 - 2013

N2 - In this work we present III-V device performance and its variability under various design and process parameters, as compared to Si devices, using MC simulation. III-V device compact/BSIM models are developed, including geometry-dependent parasitic RC. Compared to its Si counterpart, III-V devices exhibit superior performance in Ion, ring oscillator delay (t pd) and SRAM read time (tread). We calculated the N it target for mitigating increments of Ioff and subthreshold slopes. For both Si and III-V sub-7nm technology optimization, we propose a direction for technology design to improve performance and area scaling without variability penalty.

AB - In this work we present III-V device performance and its variability under various design and process parameters, as compared to Si devices, using MC simulation. III-V device compact/BSIM models are developed, including geometry-dependent parasitic RC. Compared to its Si counterpart, III-V devices exhibit superior performance in Ion, ring oscillator delay (t pd) and SRAM read time (tread). We calculated the N it target for mitigating increments of Ioff and subthreshold slopes. For both Si and III-V sub-7nm technology optimization, we propose a direction for technology design to improve performance and area scaling without variability penalty.

UR - http://www.scopus.com/inward/record.url?scp=84894386475&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84894386475&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2013.6724566

DO - 10.1109/IEDM.2013.6724566

M3 - Conference contribution

AN - SCOPUS:84894386475

SN - 9781479923076

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 5.3.1-5.3.4

BT - 2013 IEEE International Electron Devices Meeting, IEDM 2013

T2 - 2013 IEEE International Electron Devices Meeting, IEDM 2013

Y2 - 9 December 2013 through 11 December 2013

ER -

Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node

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