TY - GEN
T1 - Comparative Analysis of Digital STDP Learning Circuits Designed Using Counter and Shift Register
AU - Sim, Jeongyong
AU - Joo, Sunghwan
AU - Jung, Seong Ook
PY - 2019/6
Y1 - 2019/6
N2 - This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1% and 78.7% less LUTs and FFs than the shift register based circuit, respectively.
AB - This paper presents comparative analysis of digital STDP learning circuits designed using counter and shift register for spiking neural network (SNN). In addition, it is possible for the implemented STDP learning circuits to operate when two or more spikes occur at the same time. The conventional Von Neumann architecture has limitations such as speed bottleneck because the deep learning requires a lot of parallel data processing. In order to solve this problem, the researches on SNN similar to the human neural network have been widely performed. In this paper, the unsupervised spike-timing-dependent-plasticity (STDP) circuits designed for SNN system are studied. The circuits are implemented on a Kintex Ultra Scale FPGA. The implemented counter based STDP learning circuit consumes 1.6 times less power than the shift register based STDP, and uses 73.1% and 78.7% less LUTs and FFs than the shift register based circuit, respectively.
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U2 - 10.1109/ITC-CSCC.2019.8793424
DO - 10.1109/ITC-CSCC.2019.8793424
M3 - Conference contribution
T3 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
BT - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019
Y2 - 23 June 2019 through 26 June 2019
ER -