@inproceedings{623e7f13f21542029e4382e39e8faa73,
title = "CMOS scaling with III-V channels for improved performance and low power",
abstract = "The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on 200mm Si MOSFET process flow is presented using an industry standard toolset. Statistically significant data shows that III-V devices can be processed on a Si line with controlled contamination, good uniformity and yield. The Lg = 500 nm device has a drive current of 471 μA/μm (Vgs = Vds = 1V) and intrinsic transconductance of 1005 μS/um.",
author = "Hill, {R. J.W.} and J. Oh and C. Park and J. Barnett and J. Price and J. Huang and N. Goel and Loh, {W. Y.} and P. Kirsch and P. Majhi and R. Jammy",
year = "2011",
doi = "10.1149/1.3569926",
language = "English",
isbn = "9781566778640",
series = "ECS Transactions",
number = "3",
pages = "335--344",
booktitle = "Dielectrics in Nanosystems -and- Graphene, Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications 3",
edition = "3",
note = "Graphene Ge/III-V, Nanowires and Emerging Materials for Post-CMOS Applications - 3 - 219th ECS Meeting ; Conference date: 02-05-2011 Through 04-05-2011",
}