CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction

Brian E. Cossa; Wei Yip Loh; Jungwoo Oh; Greg Smith; Casey Smith; Hemant Adhikari; Barry Sassman; Srivatsan Parthasarathy; Joel Barnett; Prashant Majhi; Robert M. Wallacea; Jiyoung Kim; Raj Jammy

CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction

Brian E. Cossa, Wei Yip Loh, Jungwoo Oh, Greg Smith, Casey Smith, Hemant Adhikari, Barry Sassman, Srivatsan Parthasarathy, Joel Barnett, Prashant Majhi, Robert M. Wallacea, Jiyoung Kim, Raj Jammy

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO ₂/high-κ dipoles resulting in SBH ≤ 0.1 eV from the conduction band-edge (CBE) and SBH ≤ 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO _x/SiO ₂ and LaO _x/SiO ₂, respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.

Original language	English
Title of host publication	2009 Symposium on VLSI Technology, VLSIT 2009
Pages	104-105
Number of pages	2
Publication status	Published - 2009
Event	2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2009 Symposium on VLSI Technology, VLSIT 2009
Country/Territory	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

Cossa, B. E., Loh, W. Y., Oh, J., Smith, G., Smith, C., Adhikari, H., Sassman, B., Parthasarathy, S., Barnett, J., Majhi, P., Wallacea, R. M., Kim, J., & Jammy, R. (2009). CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 104-105). [5200650] (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{4affc35fd7ff48be923e8256f32e5e44,

title = "CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction",

abstract = "We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2/high-κ dipoles resulting in SBH ≤ 0.1 eV from the conduction band-edge (CBE) and SBH ≤ 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x/SiO 2 and LaO x/SiO 2, respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.",

author = "Cossa, {Brian E.} and Loh, {Wei Yip} and Jungwoo Oh and Greg Smith and Casey Smith and Hemant Adhikari and Barry Sassman and Srivatsan Parthasarathy and Joel Barnett and Prashant Majhi and Wallacea, {Robert M.} and Jiyoung Kim and Raj Jammy",

year = "2009",

language = "English",

isbn = "9784863480094",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "104--105",

booktitle = "2009 Symposium on VLSI Technology, VLSIT 2009",

note = "2009 Symposium on VLSI Technology, VLSIT 2009 ; Conference date: 16-06-2009 Through 18-06-2009",

}

Cossa, BE, Loh, WY, Oh, J, Smith, G, Smith, C, Adhikari, H, Sassman, B, Parthasarathy, S, Barnett, J, Majhi, P, Wallacea, RM, Kim, J & Jammy, R 2009, CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction. in 2009 Symposium on VLSI Technology, VLSIT 2009., 5200650, Digest of Technical Papers - Symposium on VLSI Technology, pp. 104-105, 2009 Symposium on VLSI Technology, VLSIT 2009, Kyoto, Japan, 09/6/16.

CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction. / Cossa, Brian E.; Loh, Wei Yip; Oh, Jungwoo et al.
2009 Symposium on VLSI Technology, VLSIT 2009. 2009. p. 104-105 5200650 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction

AU - Cossa, Brian E.

AU - Loh, Wei Yip

AU - Oh, Jungwoo

AU - Smith, Greg

AU - Smith, Casey

AU - Adhikari, Hemant

AU - Sassman, Barry

AU - Parthasarathy, Srivatsan

AU - Barnett, Joel

AU - Majhi, Prashant

AU - Wallacea, Robert M.

AU - Kim, Jiyoung

AU - Jammy, Raj

PY - 2009

Y1 - 2009

N2 - We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2/high-κ dipoles resulting in SBH ≤ 0.1 eV from the conduction band-edge (CBE) and SBH ≤ 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x/SiO 2 and LaO x/SiO 2, respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.

AB - We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2/high-κ dipoles resulting in SBH ≤ 0.1 eV from the conduction band-edge (CBE) and SBH ≤ 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x/SiO 2 and LaO x/SiO 2, respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.

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M3 - Conference contribution

AN - SCOPUS:71049131199

SN - 9784863480094

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 104

EP - 105

BT - 2009 Symposium on VLSI Technology, VLSIT 2009

T2 - 2009 Symposium on VLSI Technology, VLSIT 2009

Y2 - 16 June 2009 through 18 June 2009

ER -

CMOS band-edge Schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction

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