Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

Jaewon Jang; Minho Cheong; Jin Ho Ahn; Sung Kyu Lim; Sungho Kang

doi:10.1109/TVLSI.2016.2623810

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

Jaewon Jang, Minho Cheong, Jin Ho Ahn, Sung Kyu Lim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.

Original language	English
Article number	7747508
Pages (from-to)	1178-1182
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	25
Issue number	3
DOIs	https://doi.org/10.1109/TVLSI.2016.2623810
Publication status	Published - 2017 Mar

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2016.2623810

Cite this

@article{134393ba79e849dda053e2f8b3db19c1,

title = "Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation",

abstract = "A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.",

author = "Jaewon Jang and Minho Cheong and Ahn, {Jin Ho} and Lim, {Sung Kyu} and Sungho Kang",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.",

year = "2017",

month = mar,

doi = "10.1109/TVLSI.2016.2623810",

language = "English",

volume = "25",

pages = "1178--1182",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

AU - Jang, Jaewon

AU - Cheong, Minho

AU - Ahn, Jin Ho

AU - Lim, Sung Kyu

AU - Kang, Sungho

PY - 2017/3

Y1 - 2017/3

N2 - A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.

AB - A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.

UR - http://www.scopus.com/inward/record.url?scp=84996614783&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84996614783&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2016.2623810

DO - 10.1109/TVLSI.2016.2623810

M3 - Article

AN - SCOPUS:84996614783

SN - 1063-8210

VL - 25

SP - 1178

EP - 1182

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 3

M1 - 7747508

ER -

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

Abstract

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