Broadcast scan compression based on deterministic pattern generation algorithm

Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

As advances in technology make integrating more transistors on a single integrated circuit (IC) feasible, test data volume becomes one of major factors of testing system-on-chips (SoCs). The large volume of test data leads to increasing test application time and needs more expensive Automatic test equipment (ATE) with high memory. In this paper, we present broadcast scan compression based on deterministic pattern generation algorithm to reduce the volume of test data. The proposed method further improves compression ratio of the volume of test data by exploiting advances of both broadcast scan compression and pattern generation using linear feedback shift register (LFSR). The volume of test data can be reduced by feeding multiple scan chains from a few LFSRs and by compressing the data using LFSRs. ISCAS'89 benchmark circuits verify the proposed method and the experimental results show that the compression ratio is up to 10× which means test application time also is reduced extremely.

Original languageEnglish
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
PublisherIEEE Computer Society
Pages449-453
Number of pages5
ISBN (Electronic)9781509054046
DOIs
Publication statusPublished - 2017 May 2
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: 2017 Mar 142017 Mar 15

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other18th International Symposium on Quality Electronic Design, ISQED 2017
Country/TerritoryUnited States
CitySanta Clara
Period17/3/1417/3/15

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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