Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM

Choongkeun Lee; Taegun Yim; Hongil Yoon

doi:10.1109/TENCON.2018.8650337

Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM

Choongkeun Lee, Taegun Yim, Hongil Yoon

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A bit-line sense amplifier using PMOS charge transfer pre-sensing (CTPS) circuit is proposed. The CTPS circuit using charge sharing operation between lines which have different capacitance is useful for increasing small bit-line voltage differences. The PMOS latch transistors of CTPS circuit are used for pre-sensing operation and pull-up latching operation. Because the PMOS latch transistors are used mutually, area overhead of the CTPS is minimized. The PMOS CTPS circuit increases the small bit-line voltage difference and the output voltage difference of the CTPS circuit becomes the input voltage difference of the latch sense amplifier. Using the PMOS CTPS circuit, the speed of read operation and the reliability of the read operation is improved. The performance of the proposed scheme is verified by the simulation using a 45 nm process.

Original language	English
Title of host publication	Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1357-1361
Number of pages	5
ISBN (Electronic)	9781538654576
DOIs	https://doi.org/10.1109/TENCON.2018.8650337
Publication status	Published - 2019 Feb 22
Event	2018 IEEE Region 10 Conference, TENCON 2018 - Jeju, Korea, Republic of Duration: 2018 Oct 28 → 2018 Oct 31

Publication series

Name	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume	2018-October
ISSN (Print)	2159-3442
ISSN (Electronic)	2159-3450

Conference

Conference	2018 IEEE Region 10 Conference, TENCON 2018
Country/Territory	Korea, Republic of
City	Jeju
Period	18/10/28 → 18/10/31

Bibliographical note

Funding Information:
The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

Funding Information:
ACKNOWLEDGMENT This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080722) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/TENCON.2018.8650337

Cite this

Lee, C., Yim, T., & Yoon, H. (2019). Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM. In Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (pp. 1357-1361). Article 8650337 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2018-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.2018.8650337

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title = "Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM",

abstract = "A bit-line sense amplifier using PMOS charge transfer pre-sensing (CTPS) circuit is proposed. The CTPS circuit using charge sharing operation between lines which have different capacitance is useful for increasing small bit-line voltage differences. The PMOS latch transistors of CTPS circuit are used for pre-sensing operation and pull-up latching operation. Because the PMOS latch transistors are used mutually, area overhead of the CTPS is minimized. The PMOS CTPS circuit increases the small bit-line voltage difference and the output voltage difference of the CTPS circuit becomes the input voltage difference of the latch sense amplifier. Using the PMOS CTPS circuit, the speed of read operation and the reliability of the read operation is improved. The performance of the proposed scheme is verified by the simulation using a 45 nm process.",

author = "Choongkeun Lee and Taegun Yim and Hongil Yoon",

note = "Funding Information: The EDA tool was supported by the IC Design Education Center (IDEC), Korea. Funding Information: ACKNOWLEDGMENT This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080722) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE Region 10 Conference, TENCON 2018 ; Conference date: 28-10-2018 Through 31-10-2018",

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doi = "10.1109/TENCON.2018.8650337",

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Lee, C, Yim, T & Yoon, H 2019, Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM. in Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference., 8650337, IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 2018-October, Institute of Electrical and Electronics Engineers Inc., pp. 1357-1361, 2018 IEEE Region 10 Conference, TENCON 2018, Jeju, Korea, Republic of, 18/10/28. https://doi.org/10.1109/TENCON.2018.8650337

Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM. / Lee, Choongkeun; Yim, Taegun; Yoon, Hongil.
Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 1357-1361 8650337 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: The EDA tool was supported by the IC Design Education Center (IDEC), Korea. Funding Information: ACKNOWLEDGMENT This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (10080722) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Publisher Copyright: © 2018 IEEE.

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Y1 - 2019/2/22

N2 - A bit-line sense amplifier using PMOS charge transfer pre-sensing (CTPS) circuit is proposed. The CTPS circuit using charge sharing operation between lines which have different capacitance is useful for increasing small bit-line voltage differences. The PMOS latch transistors of CTPS circuit are used for pre-sensing operation and pull-up latching operation. Because the PMOS latch transistors are used mutually, area overhead of the CTPS is minimized. The PMOS CTPS circuit increases the small bit-line voltage difference and the output voltage difference of the CTPS circuit becomes the input voltage difference of the latch sense amplifier. Using the PMOS CTPS circuit, the speed of read operation and the reliability of the read operation is improved. The performance of the proposed scheme is verified by the simulation using a 45 nm process.

AB - A bit-line sense amplifier using PMOS charge transfer pre-sensing (CTPS) circuit is proposed. The CTPS circuit using charge sharing operation between lines which have different capacitance is useful for increasing small bit-line voltage differences. The PMOS latch transistors of CTPS circuit are used for pre-sensing operation and pull-up latching operation. Because the PMOS latch transistors are used mutually, area overhead of the CTPS is minimized. The PMOS CTPS circuit increases the small bit-line voltage difference and the output voltage difference of the CTPS circuit becomes the input voltage difference of the latch sense amplifier. Using the PMOS CTPS circuit, the speed of read operation and the reliability of the read operation is improved. The performance of the proposed scheme is verified by the simulation using a 45 nm process.

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Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM

Abstract

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Bibliographical note

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