Bit-error rate improvement of TLC NAND Flash using state re-ordering

Ik Joon Chang; Joon Sung Yang

doi:10.1587/elex.9.1775

Bit-error rate improvement of TLC NAND Flash using state re-ordering

Ik Joon Chang, Joon Sung Yang

College of Engineering

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

In scaled technologies, large cell-to-cell interference and FN tunneling disturbance degrade threshold voltage (Vt) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P1 ~ P7) in the narrow V_t window, incurring large bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of Vt window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent Vt window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.

Original language	English
Pages (from-to)	1775-1779
Number of pages	5
Journal	ieice electronics express
Volume	9
Issue number	23
DOIs	https://doi.org/10.1587/elex.9.1775
Publication status	Published - 2012

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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abstract = "In scaled technologies, large cell-to-cell interference and FN tunneling disturbance degrade threshold voltage (Vt) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P1 ~ P7) in the narrow Vt window, incurring large bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of Vt window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent Vt window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.",

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Bit-error rate improvement of TLC NAND Flash using state re-ordering

Abstract

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