Bit-error rate improvement of TLC NAND Flash using state re-ordering

Ik Joon Chang, Joon Sung Yang

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


In scaled technologies, large cell-to-cell interference and FN tunneling disturbance degrade threshold voltage (Vt) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P1 ~ P7) in the narrow Vt window, incurring large bit-error rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of Vt window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent Vt window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.

Original languageEnglish
Pages (from-to)1775-1779
Number of pages5
Journalieice electronics express
Issue number23
Publication statusPublished - 2012

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


Dive into the research topics of 'Bit-error rate improvement of TLC NAND Flash using state re-ordering'. Together they form a unique fingerprint.

Cite this