BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

Nohjung Kwak; Sang Tae Ahn; Hyung Soon Park; Seo Min Kim; Jin Ki Jung; Gyu Hyun Kim; Geun Young Choi; Dong Chul Koo; Tae Oh Jung; Ja Chun Ku; Jae Kwan Jung; Jinwoong Kim; Sungwook Park; Hyunchul Sohn; Soo Hyun Kim

doi:10.1109/iitc.2007.382367

BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

Nohjung Kwak, Sang Tae Ahn, Hyung Soon Park, Seo Min Kim, Jin Ki Jung, Gyu Hyun Kim, Geun Young Choi, Dong Chul Koo, Tae Oh Jung, Ja Chun Ku, Jae Kwan Jung, Jinwoong Kim, Sungwook Park, Hyunchul Sohn, Soo Hyun Kim

Department of Materials Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (M1 single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.

Original language	English
Title of host publication	Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers
Publisher	IEEE Computer Society
Pages	150-152
Number of pages	3
ISBN (Print)	1424410703, 9781424410705
DOIs	https://doi.org/10.1109/iitc.2007.382367
Publication status	Published - 2007
Event	IEEE 2007 International Interconnect Technology Conference, IITC - Burlingame, CA, United States Duration: 2007 Jun 4 → 2007 Jun 6

Publication series

Name	Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Other

Other	IEEE 2007 International Interconnect Technology Conference, IITC
Country/Territory	United States
City	Burlingame, CA
Period	07/6/4 → 07/6/6

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Condensed Matter Physics

Access to Document

10.1109/iitc.2007.382367

Cite this

Kwak, N., Ahn, S. T., Park, H. S., Kim, S. M., Jung, J. K., Kim, G. H., Choi, G. Y., Koo, D. C., Jung, T. O., Ku, J. C., Jung, J. K., Kim, J., Park, S., Sohn, H., & Kim, S. H. (2007). BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability. In Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers (pp. 150-152). [4263679] (Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers). IEEE Computer Society. https://doi.org/10.1109/iitc.2007.382367

Kwak, Nohjung ; Ahn, Sang Tae ; Park, Hyung Soon et al. / BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability. Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers. IEEE Computer Society, 2007. pp. 150-152 (Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers).

@inproceedings{656cefbbe5e7431286cc65d6beb1f544,

title = "BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability",

abstract = "For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (M1 single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.",

author = "Nohjung Kwak and Ahn, {Sang Tae} and Park, {Hyung Soon} and Kim, {Seo Min} and Jung, {Jin Ki} and Kim, {Gyu Hyun} and Choi, {Geun Young} and Koo, {Dong Chul} and Jung, {Tae Oh} and Ku, {Ja Chun} and Jung, {Jae Kwan} and Jinwoong Kim and Sungwook Park and Hyunchul Sohn and Kim, {Soo Hyun}",

year = "2007",

doi = "10.1109/iitc.2007.382367",

language = "English",

isbn = "1424410703",

series = "Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers",

publisher = "IEEE Computer Society",

pages = "150--152",

booktitle = "Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers",

address = "United States",

note = "IEEE 2007 International Interconnect Technology Conference, IITC ; Conference date: 04-06-2007 Through 06-06-2007",

}

Kwak, N, Ahn, ST, Park, HS, Kim, SM, Jung, JK, Kim, GH, Choi, GY, Koo, DC, Jung, TO, Ku, JC, Jung, JK, Kim, J, Park, S, Sohn, H & Kim, SH 2007, BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability. in Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers., 4263679, Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers, IEEE Computer Society, pp. 150-152, IEEE 2007 International Interconnect Technology Conference, IITC, Burlingame, CA, United States, 07/6/4. https://doi.org/10.1109/iitc.2007.382367

BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability. / Kwak, Nohjung; Ahn, Sang Tae; Park, Hyung Soon et al.
Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers. IEEE Computer Society, 2007. p. 150-152 4263679 (Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

AU - Kwak, Nohjung

AU - Ahn, Sang Tae

AU - Park, Hyung Soon

AU - Kim, Seo Min

AU - Jung, Jin Ki

AU - Kim, Gyu Hyun

AU - Choi, Geun Young

AU - Koo, Dong Chul

AU - Jung, Tae Oh

AU - Ku, Ja Chun

AU - Jung, Jae Kwan

AU - Kim, Jinwoong

AU - Park, Sungwook

AU - Sohn, Hyunchul

AU - Kim, Soo Hyun

PY - 2007

Y1 - 2007

N2 - For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (M1 single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.

AB - For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (M1 single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.

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DO - 10.1109/iitc.2007.382367

M3 - Conference contribution

AN - SCOPUS:34748844701

SN - 1424410703

SN - 9781424410705

T3 - Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

SP - 150

EP - 152

BT - Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

PB - IEEE Computer Society

T2 - IEEE 2007 International Interconnect Technology Conference, IITC

Y2 - 4 June 2007 through 6 June 2007

ER -

Kwak N, Ahn ST, Park HS, Kim SM, Jung JK, Kim GH et al. BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability. In Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers. IEEE Computer Society. 2007. p. 150-152. 4263679. (Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers). doi: 10.1109/iitc.2007.382367

BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability

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