Automatic synthesis for the reachability of process systems with a model checking algorithm

This study focuses on the applications of model checking techniques in automatic synthesis for the reachability of process systems. Model checking is an automatic method used to verify if a circuit or a condition, expressed as a concurrent transition system, satisfies a set of properties. The strength of this method lies in its ability to synthesize a feasible sequence with a counterexample and to verify its correctness using temporal logics such as computation tree logic (CTL) simultaneously. These challengeable approaches are implemented in a commercial software package (UPPAAL) using graphical discrete modeling, automata theory, and CTL to automate the synthesis for the reachability of process systems. Three use cases of interest in computer-aided engineering due to the difficulty involved in synthesizing them manually are explored. In the first use case, the optimal operating procedure according to the objective function of a paper mill process is synthesized. In the second use case, a challengeable attempt to optimize supply chain networks is tested. In the third use case, alternative pathways with the desired constraints are found in biochemical networks. The paper also explains how the proposed model checking method can be used efficiently in graphical modeling with automata theory to automatically synthesize process systems counterexamples using CTL by means of the case studies.