Area-optimal sensing circuit designs in deep submicrometer STT-RAM

Sara Choi; Taehui Na; Seong Ook Jung; Jung Pill Kim; Seung H. Kang

doi:10.1109/ISCAS.2016.7527473

Area-optimal sensing circuit designs in deep submicrometer STT-RAM

Sara Choi, Taehui Na, Seong Ook Jung, Jung Pill Kim, Seung H. Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1246-1249
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527473
Publication status	Published - 2016 Jul 29
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 2016 May 22 → 2016 May 25

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Other

Other	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	16/5/22 → 16/5/25

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2016.7527473

Cite this

Choi, S., Na, T., Jung, S. O., Kim, J. P., & Kang, S. H. (2016). Area-optimal sensing circuit designs in deep submicrometer STT-RAM. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 1246-1249). Article 7527473 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527473

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abstract = "As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.",

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author = "Sara Choi and Taehui Na and Jung, {Seong Ook} and Kim, {Jung Pill} and Kang, {Seung H.}",

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Choi, S, Na, T, Jung, SO, Kim, JP & Kang, SH 2016, Area-optimal sensing circuit designs in deep submicrometer STT-RAM. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527473, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, Institute of Electrical and Electronics Engineers Inc., pp. 1246-1249, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 16/5/22. https://doi.org/10.1109/ISCAS.2016.7527473

Area-optimal sensing circuit designs in deep submicrometer STT-RAM. / Choi, Sara; Na, Taehui; Jung, Seong Ook et al.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1246-1249 7527473 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Area-optimal sensing circuit designs in deep submicrometer STT-RAM

AU - Choi, Sara

AU - Na, Taehui

AU - Jung, Seong Ook

AU - Kim, Jung Pill

AU - Kang, Seung H.

PY - 2016/7/29

Y1 - 2016/7/29

N2 - As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

AB - As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

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Area-optimal sensing circuit designs in deep submicrometer STT-RAM

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