Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

Janghee Lee; Seongjoo Lee; Jaeseok Kim

doi:10.1109/TENCON.1999.818410

Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

Janghee Lee, Seongjoo Lee, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

Original language	English
Title of host publication	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	301-304
Number of pages	4
ISBN (Electronic)	0780357396, 9780780357396
DOIs	https://doi.org/10.1109/TENCON.1999.818410
Publication status	Published - 1999
Event	1999 IEEE Region 10 Conference, TENCON 1999 - Cheju Island, Korea, Republic of Duration: 1999 Sept 15 → 1999 Sept 17

Publication series

Name	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume	1
ISSN (Print)	2159-3442
ISSN (Electronic)	2159-3450

Other

Other	1999 IEEE Region 10 Conference, TENCON 1999
Country/Territory	Korea, Republic of
City	Cheju Island
Period	99/9/15 → 99/9/17

Bibliographical note

Publisher Copyright:
© 1999 IEEE.

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/TENCON.1999.818410

Cite this

Lee, J., Lee, S., & Kim, J. (1999). Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. In IEEE Region 10 Annual International Conference, Proceedings/TENCON (pp. 301-304). (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TENCON.1999.818410

Lee, Janghee ; Lee, Seongjoo ; Kim, Jaeseok. / Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 301-304 (IEEE Region 10 Annual International Conference, Proceedings/TENCON).

@inproceedings{0279a9b09a65488e968f5918c531ff96,

title = "Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM",

abstract = "a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.",

author = "Janghee Lee and Seongjoo Lee and Jaeseok Kim",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1999 IEEE Region 10 Conference, TENCON 1999 ; Conference date: 15-09-1999 Through 17-09-1999",

year = "1999",

doi = "10.1109/TENCON.1999.818410",

language = "English",

series = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

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Lee, J, Lee, S & Kim, J 1999, Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. in IEEE Region 10 Annual International Conference, Proceedings/TENCON. IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 301-304, 1999 IEEE Region 10 Conference, TENCON 1999, Cheju Island, Korea, Republic of, 99/9/15. https://doi.org/10.1109/TENCON.1999.818410

Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. / Lee, Janghee; Lee, Seongjoo; Kim, Jaeseok.
IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc., 1999. p. 301-304 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

AU - Lee, Janghee

AU - Lee, Seongjoo

AU - Kim, Jaeseok

PY - 1999

Y1 - 1999

N2 - a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

AB - a We propose a new architecture of fast symbol timing synchronization system which consists of a received signal power detector, a correlation power detector and a peak detector. These blocks have some shared hardware blocks to reduce the hardware complexity. A two-step peak detection hardware architecture is proposed to acquire the symbol timing synchronization. The proposed design can detect the correct FFT starting point within three symbols using the first two reference symbols in wireless ATM. Consequently, the proposed system is very useful for burst data transmission in wireless LAN or wireless ATM systems. The proposed architecture is designed and verified in VHDL.

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U2 - 10.1109/TENCON.1999.818410

DO - 10.1109/TENCON.1999.818410

M3 - Conference contribution

AN - SCOPUS:34547573803

T3 - IEEE Region 10 Annual International Conference, Proceedings/TENCON

SP - 301

EP - 304

BT - IEEE Region 10 Annual International Conference, Proceedings/TENCON

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1999 IEEE Region 10 Conference, TENCON 1999

Y2 - 15 September 1999 through 17 September 1999

ER -

Lee J, Lee S, Kim J. Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM. In IEEE Region 10 Annual International Conference, Proceedings/TENCON. Institute of Electrical and Electronics Engineers Inc. 1999. p. 301-304. (IEEE Region 10 Annual International Conference, Proceedings/TENCON). doi: 10.1109/TENCON.1999.818410

Architecture design of a fast symbol timing synchronization system with a shared architecture for wireless ATM

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