Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM

Suk Min Kim; Byungkyu Song; Tae Woo Oh; Seong Ook Jung

doi:10.1109/PRIME.2018.8430359

Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM

Suk Min Kim, Byungkyu Song, Tae Woo Oh, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.

Original language	English
Title of host publication	PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	65-68
Number of pages	4
ISBN (Print)	9781538653869
DOIs	https://doi.org/10.1109/PRIME.2018.8430359
Publication status	Published - 2018 Aug 8
Event	14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 - Prague, Czech Republic Duration: 2018 Jul 2 → 2018 Jul 5

Publication series

Name	PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics

Other

Other	14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018
Country/Territory	Czech Republic
City	Prague
Period	18/7/2 → 18/7/5

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Instrumentation

Access to Document

10.1109/PRIME.2018.8430359

Cite this

Kim, S. M., Song, B., Oh, T. W., & Jung, S. O. (2018). Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. In PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics (pp. 65-68). Article 8430359 (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME.2018.8430359

Kim, Suk Min ; Song, Byungkyu ; Oh, Tae Woo et al. / Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 65-68 (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics).

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title = "Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM",

abstract = "Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.",

keywords = "DRAM, latch-delay failure, low-power, offset failure, voltage latched sense amplifier",

author = "Kim, {Suk Min} and Byungkyu Song and Oh, {Tae Woo} and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018 ; Conference date: 02-07-2018 Through 05-07-2018",

year = "2018",

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doi = "10.1109/PRIME.2018.8430359",

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series = "PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics",

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Kim, SM, Song, B, Oh, TW & Jung, SO 2018, Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. in PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics., 8430359, PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics, Institute of Electrical and Electronics Engineers Inc., pp. 65-68, 14th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2018, Prague, Czech Republic, 18/7/2. https://doi.org/10.1109/PRIME.2018.8430359

Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. / Kim, Suk Min; Song, Byungkyu; Oh, Tae Woo et al.
PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc., 2018. p. 65-68 8430359 (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM

AU - Kim, Suk Min

AU - Song, Byungkyu

AU - Oh, Tae Woo

AU - Jung, Seong Ook

PY - 2018/8/8

Y1 - 2018/8/8

N2 - Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.

AB - Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability.

KW - DRAM

KW - latch-delay failure

KW - low-power

KW - offset failure

KW - voltage latched sense amplifier

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Kim SM, Song B, Oh TW, Jung SO. Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. In PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics. Institute of Electrical and Electronics Engineers Inc. 2018. p. 65-68. 8430359. (PRIME 2018 - 14th Conference on Ph.D. Research in Microelectronics and Electronics). doi: 10.1109/PRIME.2018.8430359

Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM

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